include/bsp/irq.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMCycVIRQ
0007  */
0008
0009 /*
0010  * Copyright (c) 2013 embedded brains GmbH & Co. KG
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 #ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H
0035 #define LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H
0036
0037 #ifndef ASM
0038
0039 #include <rtems/irq.h>
0040 #include <rtems/irq-extension.h>
0041
0042 #include <bsp/arm-a9mpcore-irq.h>
0043 #include <dev/irq/arm-gic-irq.h>
0044 #include <bsp/alt_interrupt_common.h>
0045
0046 #ifdef __cplusplus
0047 extern "C" {
0048 #endif /* __cplusplus */
0049
0050 /**
0051  * @defgroup RTEMSBSPsARMCycVIRQ Interrupt Support
0052  *
0053  * @ingroup RTEMSBSPsARMCycV
0054  *
0055  * @ingroup RTEMSImplClassicIntr
0056  *
0057  * @brief Intel Cyclone V Interrupt Support.
0058  *
0059  * @{
0060  */
0061
0062 /* Use interrupt IDs as defined in alt_interrupt_common.h */
0063 #define BSP_INTERRUPT_VECTOR_COUNT \
0064   (ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ + 1)
0065
0066 /** @} */
0067
0068 #ifdef __cplusplus
0069 }
0070 #endif /* __cplusplus */
0071
0072 #endif /* ASM */
0073
0074 #endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H */