include/bsp/alt_reset_manager.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMCycVContrib
0005  */
0006
0007 /*! \file
0008  *  Altera - SoC Reset Manager
0009  */
0010
0011 /******************************************************************************
0012 *
0013 * Copyright 2013 Altera Corporation. All Rights Reserved.
0014 *
0015 * Redistribution and use in source and binary forms, with or without
0016 * modification, are permitted provided that the following conditions are met:
0017 *
0018 * 1. Redistributions of source code must retain the above copyright notice,
0019 * this list of conditions and the following disclaimer.
0020 *
0021 * 2. Redistributions in binary form must reproduce the above copyright notice,
0022 * this list of conditions and the following disclaimer in the documentation
0023 * and/or other materials provided with the distribution.
0024 *
0025 * 3. The name of the author may not be used to endorse or promote products
0026 * derived from this software without specific prior written permission.
0027 *
0028 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
0029 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0030 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
0031 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0032 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
0033 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0034 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0035 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0036 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
0037 * OF SUCH DAMAGE.
0038 *
0039 ******************************************************************************/
0040
0041 #ifndef __ALT_RESET_MGR_H__
0042 #define __ALT_RESET_MGR_H__
0043
0044 #include "hwlib.h"
0045 #include <stdbool.h>
0046
0047 #ifdef __cplusplus
0048 extern "C"
0049 {
0050 #endif  /* __cplusplus */
0051
0052 /*! \addtogroup RST_MGR The Reset Manager
0053  *
0054  * The Reset Manager API defines functions for accessing, configuring, and
0055  * controlling the HPS reset behavior.
0056  * @{
0057  */
0058
0059 /******************************************************************************/
0060 /*! \addtogroup RST_MGR_STATUS Reset Status
0061  *
0062  * This functional group provides information on various aspects of SoC reset
0063  * status and timeout events.
0064  *
0065  * @{
0066  */
0067
0068 /******************************************************************************/
0069 /*!
0070  * This type definition enumerates the set of reset causes and timeout events as
0071  * register mask values.
0072  */
0073 typedef enum ALT_RESET_EVENT_e
0074 {
0075     /*! Power-On Voltage Detector Cold Reset */
0076     ALT_RESET_EVENT_PORVOLTRST          = 0x00000001,
0077
0078     /*! nPOR Pin Cold Reset                  */
0079     ALT_RESET_EVENT_NPORPINRST          = 0x00000002,
0080
0081     /*! FPGA Core Cold Reset                 */
0082     ALT_RESET_EVENT_FPGACOLDRST         = 0x00000004,
0083
0084     /*! CONFIG_IO Cold Reset                 */
0085     ALT_RESET_EVENT_CONFIGIOCOLDRST     = 0x00000008,
0086
0087     /*! Software Cold Reset                  */
0088     ALT_RESET_EVENT_SWCOLDRST           = 0x00000010,
0089
0090     /*! nRST Pin Warm Reset                  */
0091     ALT_RESET_EVENT_NRSTPINRST          = 0x00000100,
0092
0093     /*! FPGA Core Warm Reset                 */
0094     ALT_RESET_EVENT_FPGAWARMRST         = 0x00000200,
0095
0096     /*! Software Warm Reset                  */
0097     ALT_RESET_EVENT_SWWARMRST           = 0x00000400,
0098
0099     /*! MPU Watchdog 0 Warm Reset            */
0100     ALT_RESET_EVENT_MPUWD0RST           = 0x00001000,
0101
0102     /*! MPU Watchdog 1 Warm Reset            */
0103     ALT_RESET_EVENT_MPUWD1RST           = 0x00002000,
0104
0105     /*! L4 Watchdog 0 Warm Reset             */
0106     ALT_RESET_EVENT_L4WD0RST            = 0x00004000,
0107
0108     /*! L4 Watchdog 1 Warm Reset             */
0109     ALT_RESET_EVENT_L4WD1RST            = 0x00008000,
0110
0111     /*! FPGA Core Debug Reset                */
0112     ALT_RESET_EVENT_FPGADBGRST          = 0x00040000,
0113
0114     /*! DAP Debug Reset                      */
0115     ALT_RESET_EVENT_CDBGREQRST          = 0x00080000,
0116
0117     /*! SDRAM Self-Refresh Timeout           */
0118     ALT_RESET_EVENT_SDRSELFREFTIMEOUT   = 0x01000000,
0119
0120     /*! FPGA manager handshake Timeout       */
0121     ALT_RESET_EVENT_FPGAMGRHSTIMEOUT    = 0x02000000,
0122
0123     /*! SCAN manager handshake Timeout       */
0124     ALT_RESET_EVENT_SCANHSTIMEOUT       = 0x04000000,
0125
0126     /*! FPGA handshake Timeout               */
0127     ALT_RESET_EVENT_FPGAHSTIMEOUT       = 0x08000000,
0128
0129     /*! ETR Stall Timeout                    */
0130     ALT_RESET_EVENT_ETRSTALLTIMEOUT     = 0x10000000
0131 } ALT_RESET_EVENT_t;
0132
0133 /******************************************************************************/
0134 /*!
0135  * Gets the reset and timeout events that caused the last reset.
0136  *
0137  * The ALT_RESET_EVENT_t enumeration values should be used to selectively
0138  * examine the returned reset cause(s).
0139  *
0140  * \returns     A mask of the reset and/or timeout events that caused the last
0141  *              reset.
0142  */
0143 uint32_t alt_reset_event_get(void);
0144
0145 /******************************************************************************/
0146 /*!
0147  * Clears the reset and timeout events that caused the last reset.
0148  *
0149  * \param       event_mask
0150  *              A mask of the selected reset and timeout events to clear in the
0151  *              Reset Manager \e stat register. The mask selection can be formed
0152  *              using the ALT_RESET_EVENT_t enumeration values.
0153  *
0154  * \retval      ALT_E_SUCCESS   The operation was succesful.
0155  * \retval      ALT_E_ERROR     The operation failed.
0156  */
0157 ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask);
0158
0159 /*! @} */
0160
0161 /******************************************************************************/
0162 /*! \addtogroup RST_MGR_CTRL Reset Control
0163  *
0164  * This functional group provides global and selective reset control for the SoC
0165  * and its constituent modules.
0166  *
0167  * @{
0168  */
0169
0170 /******************************************************************************/
0171 /*!
0172  * Initiate a cold reset of the SoC.
0173  *
0174  * If this function is successful, then it should never return.
0175  *
0176  * \retval      ALT_E_SUCCESS   The operation was succesful.
0177  * \retval      ALT_E_ERROR     The operation failed.
0178  */
0179 ALT_STATUS_CODE alt_reset_cold_reset(void);
0180
0181 /******************************************************************************/
0182 /*!
0183  * Initiate a warm reset of the SoC.
0184  *
0185  * Perform a hardware sequenced warm reset of the SoC. A hardware sequenced
0186  * reset handshake with certain modules can optionally be requested in an
0187  * attempt to ensure an orderly reset transition.
0188  *
0189  * \param       warm_reset_delay
0190  *              Specifies the number of cycles after the Reset Manager releases
0191  *              the Clock Manager reset before releasing any other hardware
0192  *              controlled resets. Value must be greater than 16 and less than
0193  *              256.
0194  *
0195  * \param       nRST_pin_clk_assertion
0196  *              Specifies that number of clock cycles (osc1_clk?) to externally
0197  *              assert the warm reset pin (nRST). 0 <= \e nRST_pin_clk_assertion <=
0198  *              (2**20 - 1). A value of 0 prevents any assertion of nRST.
0199  *
0200  * \param       sdram_refresh
0201  *              Controls whether the contents of SDRAM survive a hardware
0202  *              sequenced warm reset. The reset manager requests the SDRAM
0203  *              controller to put SDRAM devices into self-refresh mode before
0204  *              asserting warm reset signals. An argument value of \b true
0205  *              enables the option, \b false disables the option.
0206  *
0207  * \param       fpga_mgr_handshake
0208  *              Controls whether a handshake between the reset manager and FPGA
0209  *              manager occurs before a warm reset. The handshake is used to
0210  *              warn the FPGA manager that a warm reset is imminent so it can
0211  *              prepare for it by driving its output clock to a quiescent state
0212  *              to avoid glitches. An argument value of \b true enables the
0213  *              option, \b false disables the option.
0214  *
0215  * \param       scan_mgr_handshake
0216  *              Controls whether a handshake between the reset manager and scan
0217  *              manager occurs before a warm reset. The handshake is used to
0218  *              warn the scan manager that a warm reset is imminent so it can
0219  *              prepare for it by driving its output clock to a quiescent state
0220  *              to avoid glitches. An argument value of \b true enables the
0221  *              option, \b false disables the option.
0222  *
0223  * \param       fpga_handshake
0224  *              Controls whether a handshake between the reset manager and the
0225  *              FPGA occurs before a warm reset. The handshake is used to warn
0226  *              the FPGA that a warm reset is imminent so that the FPGA prepare
0227  *              for the reset event in soft IP. An argument value of \b true
0228  *              enables the option, \b false disables the option.
0229  *
0230  * \param       etr_stall
0231  *              Controls whether the ETR is requested to idle its AXI master
0232  *              interface (i.e. finish outstanding transactions and not initiate
0233  *              any more) to the L3 Interconnect before a warm reset. An
0234  *              argument value of \b true enables the option, \b false disables
0235  *              the option.
0236  *
0237  * \retval      ALT_E_SUCCESS   The operation was succesful.
0238  * \retval      ALT_E_ERROR     The operation failed.
0239  */
0240 ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay,
0241                                      uint32_t nRST_pin_clk_assertion,
0242                                      bool sdram_refresh,
0243                                      bool fpga_mgr_handshake,
0244                                      bool scan_mgr_handshake,
0245                                      bool fpga_handshake,
0246                                      bool etr_stall);
0247
0248 #if 0
0249 /*! \addtogroup RST_MGR_MPU
0250  *
0251  * This functional group provides reset control for the Cortex-A9 MPU module.
0252  *
0253  * @{
0254  */
0255
0256 /*! @} */
0257
0258 /*! \addtogroup RST_MGR_PERIPH
0259  *
0260  * This functional group provides inidividual reset control for the HPS
0261  * peripheral modules.
0262  *
0263  * @{
0264  */
0265
0266 /*! @} */
0267
0268 /*! \addtogroup RST_MGR_BRG
0269  *
0270  * This functional group provides inidividual reset control for the bridge
0271  * interfaces between the HPS and FPGA.
0272  *
0273  * @{
0274  */
0275
0276 /*! @} */
0277
0278 /*! \addtogroup RST_MGR_MISC
0279  *
0280  * This functional group provides inidividual reset control for miscellaneous
0281  * HPS modules.
0282  *
0283  * @{
0284  */
0285
0286 /*! @} */
0287
0288 #endif
0289
0290 /*! @} */
0291
0292 /*! @} */
0293
0294 #ifdef __cplusplus
0295 }
0296 #endif  /* __cplusplus */
0297 #endif  /* __ALT_RESET_MGR_H__ */