include/bsp/alt_qspi_private.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMCycVContrib
0005  */
0006
0007 /******************************************************************************
0008  *
0009  * Copyright 2013 Altera Corporation. All Rights Reserved.
0010  *
0011  * Redistribution and use in source and binary forms, with or without
0012  * modification, are permitted provided that the following conditions are met:
0013  *
0014  * 1. Redistributions of source code must retain the above copyright notice,
0015  * this list of conditions and the following disclaimer.
0016  *
0017  * 2. Redistributions in binary form must reproduce the above copyright notice,
0018  * this list of conditions and the following disclaimer in the documentation
0019  * and/or other materials provided with the distribution.
0020  *
0021  * 3. The name of the author may not be used to endorse or promote products
0022  * derived from this software without specific prior written permission.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
0025  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0026  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
0027  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0028  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
0029  * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0032  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
0033  * OF SUCH DAMAGE.
0034  *
0035  ******************************************************************************/
0036
0037 /*! \file
0038  *  Altera - QSPI Flash Controller Module
0039  */
0040
0041 #ifndef __ALT_QSPI_PRIVATE_H__
0042 #define __ALT_QSPI_PRIVATE_H__
0043
0044 #include "socal/socal.h"
0045
0046 //
0047 // This section provisions support for various flash devices.
0048 //
0049
0050 #define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1
0051
0052 /////
0053
0054 #define ALT_QSPI_PAGE_ADDR_MSK          0xFFFFFF00
0055 #define ALT_QSPI_PAGE_SIZE              0x00000100 // 256 B
0056 #define ALT_QSPI_SUBSECTOR_ADDR_MSK     0xFFFFF000
0057 #define ALT_QSPI_SUBSECTOR_SIZE         0x00001000 // 4096 B
0058 #define ALT_QSPI_SECTOR_ADDR_MSK        0xFFFF0000
0059 #define ALT_QSPI_SECTOR_SIZE            0x00010000 // 64 KiB
0060 #define ALT_QSPI_BANK_ADDR_MSK          0xFF000000
0061 #define ALT_QSPI_BANK_SIZE              0x01000000 // 16 MiB
0062
0063 #if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT
0064 #define ALT_QSPI_N25Q_DIE_ADDR_MSK      0xFE000000
0065 #define ALT_QSPI_N25Q_DIE_SIZE          0x02000000 // 32 MiB
0066 #endif
0067
0068 /////
0069
0070 // Default delay timing (in ns) for N25Q.
0071 // These values are from the N25Q handbook. The timing correctness is difficult
0072 // to test because the test setup does not feature mutliple chips.
0073 #define ALT_QSPI_TSHSL_NS_DEF       (50)
0074 #define ALT_QSPI_TSD2D_NS_DEF       (0)
0075 #define ALT_QSPI_TCHSH_NS_DEF       (4)
0076 #define ALT_QSPI_TSLCH_NS_DEF       (4)
0077
0078 /*
0079 // Default delay timing (in ns)
0080 #define ALT_QSPI_TSHSL_NS_DEF       (200)
0081 #define ALT_QSPI_TSD2D_NS_DEF       (255)
0082 #define ALT_QSPI_TCHSH_NS_DEF       (20)
0083 #define ALT_QSPI_TSLCH_NS_DEF       (20)
0084 */
0085
0086 // Flash commands
0087 #define ALT_QSPI_STIG_OPCODE_READ                 (0x03)
0088 #define ALT_QSPI_STIG_OPCODE_4BYTE_READ           (0x13)
0089 #define ALT_QSPI_STIG_OPCODE_FASTREAD             (0x0B)
0090 #define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B)
0091 #define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B)
0092 #define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO     (0xBB)
0093 #define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO     (0xEB)
0094 #define ALT_QSPI_STIG_OPCODE_PP                   (0x02)
0095 #define ALT_QSPI_STIG_OPCODE_DUAL_PP              (0xA2)
0096 #define ALT_QSPI_STIG_OPCODE_QUAD_PP              (0x32)
0097 #define ALT_QSPI_STIG_OPCODE_RDID                 (0x9F)
0098 #define ALT_QSPI_STIG_OPCODE_WREN                 (0x06)
0099 #define ALT_QSPI_STIG_OPCODE_WRDIS                (0x04)
0100 #define ALT_QSPI_STIG_OPCODE_RDSR                 (0x05)
0101 #define ALT_QSPI_STIG_OPCODE_WRSR                 (0x01)
0102 #define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE         (0x20)
0103 #define ALT_QSPI_STIG_OPCODE_SEC_ERASE            (0xD8)
0104 #define ALT_QSPI_STIG_OPCODE_BULK_ERASE           (0xC7)
0105 #define ALT_QSPI_STIG_OPCODE_DIE_ERASE            (0xC4)
0106 #define ALT_QSPI_STIG_OPCODE_CHIP_ERASE           (0x60)
0107 #define ALT_QSPI_STIG_OPCODE_RD_EXT_REG           (0xC8)
0108 #define ALT_QSPI_STIG_OPCODE_WR_EXT_REG           (0xC5)
0109 #define ALT_QSPI_STIG_OPCODE_RD_STAT_REG          (0x05)
0110 #define ALT_QSPI_STIG_OPCODE_WR_STAT_REG          (0x01)
0111 #define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE     (0xB7)
0112 #define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE      (0xE9)
0113
0114 // Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts.
0115 #if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT
0116 #define ALT_QSPI_STIG_OPCODE_RESET_EN             (0x66)
0117 #define ALT_QSPI_STIG_OPCODE_RESET_MEM            (0x99)
0118 #define ALT_QSPI_STIG_OPCODE_RDFLGSR              (0x70)
0119 #define ALT_QSPI_STIG_OPCODE_CLRFLGSR             (0x50)
0120 #define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM         (0x5A)
0121 #endif
0122
0123 // Spansion commands
0124 // #define OPCODE_ECRM                 (0xFF) // Exit continuous read mode
0125
0126 #define QSPI_READ_CLK_MHZ           (50)
0127 #define QSPI_FASTREAD_CLK_MHZ       (100)
0128
0129 // Manufacturer ID
0130 #define ALT_QSPI_STIG_RDID_JEDECID_MICRON      (0x20)
0131 #define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX     (0x20) // Same as Micron
0132 #define ALT_QSPI_STIG_RDID_JEDECID_SPANSION    (0xEF)
0133 #define ALT_QSPI_STIG_RDID_JEDECID_WINBOND     (0xEF) // Same as Spansion
0134 #define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC    (0xC2)
0135 #define ALT_QSPI_STIG_RDID_JEDECID_ATMEL       (0x1F)
0136
0137 #define ALT_QSPI_STIG_RDID_JEDECID_GET(value)    ((value >>  0) & 0xff)
0138 #define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff)
0139
0140 #define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1)
0141 #define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value)        ((value >> 7) & 0x1)
0142 #define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value)      ((value >> 7) & 0x1)
0143 #define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value)        ((value >> 5) & 0x1)
0144 #define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value)      ((value >> 4) & 0x1)
0145 #define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value)    ((value >> 1) & 0x1)
0146 #define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value)   ((value >> 0) & 0x1)
0147
0148 #define ALT_QSPI_STIG_SR_BUSY_GET(value)                  ((value >> 0) & 0x1)
0149
0150 /////
0151
0152 #define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff)
0153
0154 ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size);
0155
0156 ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout);
0157 ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy,
0158                                      uint32_t num_bytes, uint32_t * output,
0159                                      uint32_t timeout);
0160 ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy,
0161                                      uint32_t num_bytes, const uint32_t * input,
0162                                      uint32_t timeout);
0163 ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy,
0164                                        uint32_t address,
0165                                        uint32_t timeout);
0166
0167 ALT_STATUS_CODE alt_qspi_device_wren(void);
0168 ALT_STATUS_CODE alt_qspi_device_wrdis(void);
0169 ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid);
0170 ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param);
0171 ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank);
0172
0173 #endif // __ALT_PRIVATE_QSPI_H__