include/bsp/alt_mpu_registers.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMCycVContrib
0005  */
0006
0007
0008 /******************************************************************************
0009 *
0010 * Copyright 2013 Altera Corporation. All Rights Reserved.
0011 *
0012 * Redistribution and use in source and binary forms, with or without
0013 * modification, are permitted provided that the following conditions are met:
0014 *
0015 * 1. Redistributions of source code must retain the above copyright notice,
0016 * this list of conditions and the following disclaimer.
0017 *
0018 * 2. Redistributions in binary form must reproduce the above copyright notice,
0019 * this list of conditions and the following disclaimer in the documentation
0020 * and/or other materials provided with the distribution.
0021 *
0022 * 3. The name of the author may not be used to endorse or promote products
0023 * derived from this software without specific prior written permission.
0024 *
0025 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
0026 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0027 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
0028 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0029 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
0030 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0033 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
0034 * OF SUCH DAMAGE.
0035 *
0036 ******************************************************************************/
0037
0038 #ifndef __ALT_MPUSCU_H__
0039 #define __ALT_MPUSCU_H__
0040
0041
0042 #ifdef __cplusplus
0043 extern "C"
0044 {
0045 #endif  /* __cplusplus */
0046
0047
0048 /************************************************************************************************************/
0049 /*                                alt_mpuscu.h                                                                 */
0050 /*                                                                                                            */
0051 /*  Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog         */
0052 /*  Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor.    */
0053 /*                                                                                                            */
0054 /************************************************************************************************************/
0055
0056 #ifndef ALT_HPS_ADDR
0057 #define ALT_HPS_ADDR 0x00
0058 #endif
0059
0060
0061 /*     ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h            */
0062 /*    and is the address of the base of the Snoop Control Unit (SCU)                                */
0063 #define GLOBALTMR_BASE                      (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET)
0064 #define CPU_WDTGPT_TMR_BASE                 (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET)
0065 #define CPU_PRIVATE_TMR_BASE                (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET)
0066 #define CPU_INT_CTRL_BASE                   (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET)
0067 #define CPU_INT_DIST_BASE                   (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET)
0068
0069
0070             /* offsets */
0071         /* Global Timer offsets */
0072 #define GLOBALTMR_MODULE_BASE_OFFSET        0x00000200
0073 #define GLOBALTMR_CNTR_LO_REG_OFFSET        0x00000000
0074 #define GLOBALTMR_CNTR_HI_REG_OFFSET        0x00000004
0075 #define GLOBALTMR_CTRL_REG_OFFSET           0x00000008
0076 #define GLOBALTMR_INT_STAT_REG_OFFSET       0x0000000C
0077 #define GLOBALTMR_COMP_LO_REG_OFFSET        0x00000010
0078 #define GLOBALTMR_COMP_HI_REG_OFFSET        0x00000014
0079 #define GLOBALTMR_AUTOINC_REG_OFFSET        0x00000018
0080
0081 /* Global Timer bitmasks */
0082 #define GLOBALTMR_ENABLE_BIT                0x00000001
0083 #define GLOBALTMR_COMP_ENABLE_BIT           0x00000002
0084 #define GLOBALTMR_INT_ENABLE_BIT            0x00000004
0085 #define GLOBALTMR_AUTOINC_ENABLE_BIT        0x00000008
0086 #define GLOBALTMR_PS_MASK                   0x0000FF00
0087 #define GLOBALTMR_PS_SHIFT                  8
0088 #define GLOBALTMR_INT_STATUS_BIT            0x00000001
0089
0090 /* Global timer constants */
0091 #define GLOBALTMR_MAX                       0xFFFFFFFF
0092 #define GLOBALTMR_PS_MAX                    0x000000FF
0093
0094
0095 /* Private timer offsets */
0096 #define CPU_PRIV_TIMER_MODULE_BASE_OFFSET   0x00000600
0097 #define CPU_PRIV_TMR_LOAD_REG_OFFSET        0x00000000
0098 #define CPU_PRIV_TMR_CNTR_REG_OFFSET        0x00000004
0099 #define CPU_PRIV_TMR_CTRL_REG_OFFSET        0x00000008
0100 #define CPU_PRIV_TMR_INT_STATUS_REG_OFFSET  0x0000000C
0101
0102 /* Private timer bitmasks */
0103 #define CPU_PRIV_TMR_ENABLE                 0x00000001
0104 #define CPU_PRIV_TMR_AUTO_RELOAD            0x00000002
0105 #define CPU_PRIV_TMR_INT_EN                 0x00000004
0106 #define CPU_PRIV_TMR_PS_MASK                0x0000FF00
0107 #define CPU_PRIV_TMR_PS_SHIFT               8
0108 #define CPU_PRIV_TMR_INT_STATUS             0x00000001
0109
0110 /* Private timer constants */
0111 #define CPU_PRIV_TMR_MAX                    0xFFFFFFFF
0112 #define CPU_PRIV_TMR_PS_MAX                 0x000000FF
0113
0114
0115
0116     /* Watchdog timer offsets */
0117 #define WDOG_TIMER_MODULE_BASE_OFFSET       0x00000620
0118 #define WDOG_LOAD_REG_OFFSET                0x00000000
0119 #define WDOG_CNTR_REG_OFFSET                0x00000004
0120 #define WDOG_CTRL_REG_OFFSET                0x00000008
0121 #define WDOG_INTSTAT_REG_OFFSET             0x0000000C
0122 #define WDOG_RSTSTAT_REG_OFFSET             0x00000010
0123 #define WDOG_DISABLE_REG_OFFSET             0x00000014
0124
0125     /* Watchdog timer bitmasks : */
0126     /* Control Register bitmasks */
0127 #define WDOG_TMR_ENABLE                     0x00000001
0128 #define WDOG_AUTO_RELOAD                    0x00000002
0129 #define WDOG_INT_EN                         0x00000004
0130 #define WDOG_WDT_MODE                       0x00000008
0131 #define WDOG_PS_MASK                        0x0000FF00
0132 #define WDOG_PS_SHIFT                       8
0133     /* Interrupt Status Register bitmasks */
0134 #define WDOG_INT_STAT_BIT                   0x00000001
0135     /* Reset Status Register bitmasks */
0136 #define WDOG_RST_STAT_BIT                   0x00000001
0137
0138     /* Watchdog timer constants */
0139 #define WDOG_TMR_MAX                        UINT32_MAX
0140 #define WDOG_PS_MAX                         UINT8_MAX
0141 #define WDOG_DISABLE_VAL0                   0x12345678
0142 #define WDOG_DISABLE_VAL1                   0x87654321
0143
0144
0145
0146     /* Interrupt Manager offsets */
0147 /*   <Add definitions here> */
0148 #define INT_CONTROLLER_MODULE_BASE_OFFSET   0x00000100
0149 #define INT_DISTRIBUTOR_MODULE_BASE_OFFSET  0x00001000
0150 #define INT_DIST_TYPE_REG                   0x00000004
0151
0152
0153 /*  Upper bound of the MPUSCU address space  */
0154 #define MPUSCU_MAX                          0x00001FFF
0155
0156
0157
0158 #ifdef __cplusplus
0159 }
0160 #endif  /* __cplusplus */
0161
0162 #endif  /* __ALT_MPUSCU_H__ */