include/bsp/alt_interrupt_common.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMCycVContrib
0005  */
0006
0007 /******************************************************************************
0008 *
0009 * Copyright 2013 Altera Corporation. All Rights Reserved.
0010 *
0011 * Redistribution and use in source and binary forms, with or without
0012 * modification, are permitted provided that the following conditions are met:
0013 *
0014 * 1. Redistributions of source code must retain the above copyright notice,
0015 * this list of conditions and the following disclaimer.
0016 *
0017 * 2. Redistributions in binary form must reproduce the above copyright notice,
0018 * this list of conditions and the following disclaimer in the documentation
0019 * and/or other materials provided with the distribution.
0020 *
0021 * 3. The name of the author may not be used to endorse or promote products
0022 * derived from this software without specific prior written permission.
0023 *
0024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
0025 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0026 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
0027 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0028 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
0029 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0032 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
0033 * OF SUCH DAMAGE.
0034 *
0035 ******************************************************************************/
0036
0037 #ifndef __ALT_INT_COMMON_H__
0038 #define __ALT_INT_COMMON_H__
0039
0040 #include "hwlib.h"
0041 #include <stdbool.h>
0042 #include <stddef.h>
0043
0044 #ifdef __cplusplus
0045 extern "C"
0046 {
0047 #endif
0048
0049 /*!
0050  * \addtogroup INT_COMMON Interrupt Controller Common Definitions
0051  *
0052  * This module contains the definitions common to the Interrupt Controller
0053  * Low-Level API and Interrupt Controller Manager Interface.
0054  *
0055  * @{
0056  */
0057
0058 /*!
0059  * This type definition enumerates all the interrupt identification types.
0060  */
0061 typedef enum ALT_INT_INTERRUPT_e
0062 {
0063     ALT_INT_INTERRUPT_SGI0  =  0, /*!< # */
0064     ALT_INT_INTERRUPT_SGI1  =  1, /*!< # */
0065     ALT_INT_INTERRUPT_SGI2  =  2, /*!< # */
0066     ALT_INT_INTERRUPT_SGI3  =  3, /*!< # */
0067     ALT_INT_INTERRUPT_SGI4  =  4, /*!< # */
0068     ALT_INT_INTERRUPT_SGI5  =  5, /*!< # */
0069     ALT_INT_INTERRUPT_SGI6  =  6, /*!< # */
0070     ALT_INT_INTERRUPT_SGI7  =  7, /*!< # */
0071     ALT_INT_INTERRUPT_SGI8  =  8, /*!< # */
0072     ALT_INT_INTERRUPT_SGI9  =  9, /*!< # */
0073     ALT_INT_INTERRUPT_SGI10 = 10, /*!< # */
0074     ALT_INT_INTERRUPT_SGI11 = 11, /*!< # */
0075     ALT_INT_INTERRUPT_SGI12 = 12, /*!< # */
0076     ALT_INT_INTERRUPT_SGI13 = 13, /*!< # */
0077     ALT_INT_INTERRUPT_SGI14 = 14, /*!< # */
0078     ALT_INT_INTERRUPT_SGI15 = 15,
0079     /*!<
0080      * Software Generated Interrupts (SGI), 0 - 15.
0081      *  * All interrupts in this group are software triggered.
0082      */
0083
0084     ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL   = 27, /*!< # */
0085     ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE  = 29, /*!< # */
0086     ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */
0087     /*!<
0088      * Private Peripheral Interrupts (PPI) for the Global Timer, per CPU
0089      * private timer, and watchdog timer.
0090      *  * All interrupts in this group are edge triggered.
0091      */
0092
0093     ALT_INT_INTERRUPT_CPU0_PARITYFAIL         = 32, /*!< # */
0094     ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC    = 33, /*!< # */
0095     ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB     = 34, /*!< # */
0096     ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG   = 35, /*!< # */
0097     ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA  = 36, /*!< # */
0098     ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB     = 37, /*!< # */
0099     ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, /*!< # */
0100     ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG   = 39, /*!< # */
0101     ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA  = 40, /*!< # */
0102     ALT_INT_INTERRUPT_CPU0_DEFLAGS0           = 41, /*!< # */
0103     ALT_INT_INTERRUPT_CPU0_DEFLAGS1           = 42, /*!< # */
0104     ALT_INT_INTERRUPT_CPU0_DEFLAGS2           = 43, /*!< # */
0105     ALT_INT_INTERRUPT_CPU0_DEFLAGS3           = 44, /*!< # */
0106     ALT_INT_INTERRUPT_CPU0_DEFLAGS4           = 45, /*!< # */
0107     ALT_INT_INTERRUPT_CPU0_DEFLAGS5           = 46, /*!< # */
0108     ALT_INT_INTERRUPT_CPU0_DEFLAGS6           = 47,
0109     /*!<
0110      * Interrupts sourced from CPU0.
0111      *
0112      * The ALT_INT_INTERRUPT_CPU0_PARITYFAIL interrupt combines the
0113      * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
0114      * for CPU0.
0115      *
0116      *  * PARITYFAIL interrupts in this group are edge triggered.
0117      *  * DEFFLAGS interrupts in this group are level triggered.
0118      */
0119
0120     ALT_INT_INTERRUPT_CPU1_PARITYFAIL         = 48, /*!< # */
0121     ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC    = 49, /*!< # */
0122     ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB     = 50, /*!< # */
0123     ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG   = 51, /*!< # */
0124     ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA  = 52, /*!< # */
0125     ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB     = 53, /*!< # */
0126     ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, /*!< # */
0127     ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG   = 55, /*!< # */
0128     ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA  = 56, /*!< # */
0129     ALT_INT_INTERRUPT_CPU1_DEFLAGS0           = 57, /*!< # */
0130     ALT_INT_INTERRUPT_CPU1_DEFLAGS1           = 58, /*!< # */
0131     ALT_INT_INTERRUPT_CPU1_DEFLAGS2           = 59, /*!< # */
0132     ALT_INT_INTERRUPT_CPU1_DEFLAGS3           = 60, /*!< # */
0133     ALT_INT_INTERRUPT_CPU1_DEFLAGS4           = 61, /*!< # */
0134     ALT_INT_INTERRUPT_CPU1_DEFLAGS5           = 62, /*!< # */
0135     ALT_INT_INTERRUPT_CPU1_DEFLAGS6           = 63,
0136     /*!<
0137      * Interrupts sourced from CPU1.
0138      *
0139      * The ALT_INT_INTERRUPT_CPU1_PARITYFAIL interrupt combines the
0140      * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
0141      * for CPU1.
0142      *
0143      *  * PARITYFAIL interrupts in this group are edge triggered.
0144      *  * DEFFLAGS interrupts in this group are level triggered.
0145      */
0146
0147     ALT_INT_INTERRUPT_SCU_PARITYFAIL0 =  64, /*!< # */
0148     ALT_INT_INTERRUPT_SCU_PARITYFAIL1 =  65, /*!< # */
0149     ALT_INT_INTERRUPT_SCU_EV_ABORT    =  66,
0150     /*!<
0151      * Interrupts sourced from the Snoop Control Unit (SCU).
0152      *  * All interrupts in this group are edge triggered.
0153      */
0154
0155     ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ     = 67, /*!< # */
0156     ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ   = 68, /*!< # */
0157     ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */
0158     ALT_INT_INTERRUPT_L2_COMBINED_IRQ        = 70,
0159     /*!<
0160      * Interrupts sourced from the L2 Cache Controller.
0161      *
0162      * The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache
0163      * controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR,
0164      * ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts.
0165      * Consult the L2C documentation for information on these interrupts.
0166      *
0167      *  * ECC interrupts in this group are edge triggered.
0168      *  * Other interrupts in this group are level triggered.
0169      */
0170
0171     ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ =  71,
0172     /*!<
0173      * Interrupts sourced from the SDRAM Controller.
0174      *  * All interrupts in this group are level triggered.
0175      */
0176
0177     ALT_INT_INTERRUPT_F2S_FPGA_IRQ0  =  72, /*!< # */
0178     ALT_INT_INTERRUPT_F2S_FPGA_IRQ1  =  73, /*!< # */
0179     ALT_INT_INTERRUPT_F2S_FPGA_IRQ2  =  74, /*!< # */
0180     ALT_INT_INTERRUPT_F2S_FPGA_IRQ3  =  75, /*!< # */
0181     ALT_INT_INTERRUPT_F2S_FPGA_IRQ4  =  76, /*!< # */
0182     ALT_INT_INTERRUPT_F2S_FPGA_IRQ5  =  77, /*!< # */
0183     ALT_INT_INTERRUPT_F2S_FPGA_IRQ6  =  78, /*!< # */
0184     ALT_INT_INTERRUPT_F2S_FPGA_IRQ7  =  79, /*!< # */
0185     ALT_INT_INTERRUPT_F2S_FPGA_IRQ8  =  80, /*!< # */
0186     ALT_INT_INTERRUPT_F2S_FPGA_IRQ9  =  81, /*!< # */
0187     ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 =  82, /*!< # */
0188     ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 =  83, /*!< # */
0189     ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 =  84, /*!< # */
0190     ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 =  85, /*!< # */
0191     ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 =  86, /*!< # */
0192     ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 =  87, /*!< # */
0193     ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 =  88, /*!< # */
0194     ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 =  89, /*!< # */
0195     ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 =  90, /*!< # */
0196     ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 =  91, /*!< # */
0197     ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 =  92, /*!< # */
0198     ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 =  93, /*!< # */
0199     ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 =  94, /*!< # */
0200     ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 =  95, /*!< # */
0201     ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 =  96, /*!< # */
0202     ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 =  97, /*!< # */
0203     ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 =  98, /*!< # */
0204     ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 =  99, /*!< # */
0205     ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100, /*!< # */
0206     ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, /*!< # */
0207     ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, /*!< # */
0208     ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, /*!< # */
0209     ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104, /*!< # */
0210     ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, /*!< # */
0211     ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, /*!< # */
0212     ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, /*!< # */
0213     ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108, /*!< # */
0214     ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, /*!< # */
0215     ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, /*!< # */
0216     ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, /*!< # */
0217     ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112, /*!< # */
0218     ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, /*!< # */
0219     ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, /*!< # */
0220     ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, /*!< # */
0221     ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116, /*!< # */
0222     ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, /*!< # */
0223     ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, /*!< # */
0224     ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, /*!< # */
0225     ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120, /*!< # */
0226     ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, /*!< # */
0227     ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, /*!< # */
0228     ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, /*!< # */
0229     ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124, /*!< # */
0230     ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, /*!< # */
0231     ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, /*!< # */
0232     ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, /*!< # */
0233     ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128, /*!< # */
0234     ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, /*!< # */
0235     ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, /*!< # */
0236     ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, /*!< # */
0237     ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132, /*!< # */
0238     ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, /*!< # */
0239     ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, /*!< # */
0240     ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135,
0241     /*!<
0242      * Interrupt request from the FPGA logic, 0 - 63.
0243      *  * Trigger type depends on the implementation in the FPGA.
0244      */
0245
0246     ALT_INT_INTERRUPT_DMA_IRQ0                = 136, /*!< # */
0247     ALT_INT_INTERRUPT_DMA_IRQ1                = 137, /*!< # */
0248     ALT_INT_INTERRUPT_DMA_IRQ2                = 138, /*!< # */
0249     ALT_INT_INTERRUPT_DMA_IRQ3                = 139, /*!< # */
0250     ALT_INT_INTERRUPT_DMA_IRQ4                = 140, /*!< # */
0251     ALT_INT_INTERRUPT_DMA_IRQ5                = 141, /*!< # */
0252     ALT_INT_INTERRUPT_DMA_IRQ6                = 142, /*!< # */
0253     ALT_INT_INTERRUPT_DMA_IRQ7                = 143, /*!< # */
0254     ALT_INT_INTERRUPT_DMA_IRQ_ABORT           = 144, /*!< # */
0255     ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ   = 145, /*!< # */
0256     ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146,
0257     /*!<
0258      * Interrupts sourced from the DMA Controller.
0259      *  * All interrupts in this group are level triggered.
0260      */
0261
0262     ALT_INT_INTERRUPT_EMAC0_IRQ                    = 147, /*!< # */
0263     ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ   = 148, /*!< # */
0264     ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */
0265     ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ   = 150, /*!< # */
0266     ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151,
0267     /*!<
0268      * Interrupts sourced from the Ethernet MAC 0 (EMAC0).
0269      *  * All interrupts in this group are level triggered.
0270      */
0271
0272     ALT_INT_INTERRUPT_EMAC1_IRQ                    = 152, /*!< # */
0273     ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ   = 153, /*!< # */
0274     ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */
0275     ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ   = 155, /*!< # */
0276     ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156,
0277     /*!<
0278      * Interrupts sourced from the Ethernet MAC 1 (EMAC1).
0279      *  * All interrupts in this group are level triggered.
0280      */
0281
0282     ALT_INT_INTERRUPT_USB0_IRQ             = 157, /*!< # */
0283     ALT_INT_INTERRUPT_USB0_ECC_CORRECTED   = 158, /*!< # */
0284     ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159,
0285     /*!<
0286      * Interrupts sourced from the USB OTG 0.
0287      *  * All interrupts in this group are level triggered.
0288      */
0289
0290     ALT_INT_INTERRUPT_USB1_IRQ             = 160, /*!< # */
0291     ALT_INT_INTERRUPT_USB1_ECC_CORRECTED   = 161, /*!< # */
0292     ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162,
0293     /*!<
0294      * Interrupts sourced from the USB OTG 1.
0295      *  * All interrupts in this group are level triggered.
0296      */
0297
0298     ALT_INT_INTERRUPT_CAN0_STS_IRQ             = 163, /*!< # */
0299     ALT_INT_INTERRUPT_CAN0_MO_IRQ              = 164, /*!< # */
0300     ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ   = 165, /*!< # */
0301     ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166,
0302     /*!<
0303      * Interrupts sourced from the CAN Controller 0.
0304      *  * All interrupts in this group are level triggered.
0305      */
0306
0307     ALT_INT_INTERRUPT_CAN1_STS_IRQ             = 167, /*!< # */
0308     ALT_INT_INTERRUPT_CAN1_MO_IRQ              = 168, /*!< # */
0309     ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ   = 169, /*!< # */
0310     ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170,
0311     /*!<
0312      * Interrupts sourced from the CAN Controller 1.
0313      *  * All interrupts in this group are level triggered.
0314      */
0315
0316     ALT_INT_INTERRUPT_SDMMC_IRQ                   = 171, /*!< # */
0317     ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED   = 172, /*!< # */
0318     ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */
0319     ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED   = 174, /*!< # */
0320     ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175,
0321     /*!<
0322      * Interrupts sourced from the SDMMC Controller.
0323      *  * All interrupts in this group are level triggered.
0324      */
0325
0326     ALT_INT_INTERRUPT_NAND_IRQ                  = 176, /*!< # */
0327     ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ   = 177, /*!< # */
0328     ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */
0329     ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ   = 179, /*!< # */
0330     ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */
0331     ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ   = 181, /*!< # */
0332     ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182,
0333     /*!<
0334      * Interrupts sourced from the NAND Controller.
0335      *  * All interrupts in this group are level triggered.
0336      */
0337
0338     ALT_INT_INTERRUPT_QSPI_IRQ                 = 183, /*!< # */
0339     ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ   = 184, /*!< # */
0340     ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185,
0341     /*!<
0342      * Interrupts sourced from the QSPI Controller.
0343      *  * All interrupts in this group are level triggered.
0344      */
0345
0346     ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */
0347     ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */
0348     ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */
0349     ALT_INT_INTERRUPT_SPI3_IRQ = 189,
0350     /*!<
0351      * Interrupts sourced from the SPI Controllers 0 - 3.
0352      * SPI0_IRQ corresponds to SPIM0. SPI1_IRQ corresponds to SPIM1.
0353      * SPI2_IRQ corresponds to SPIS0. SPI3_IRQ corresponds to SPIS1.
0354      *  * All interrupts in this group are level triggered.
0355      */
0356
0357     ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */
0358     ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */
0359     ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */
0360     ALT_INT_INTERRUPT_I2C3_IRQ = 193,
0361     /*!<
0362      * Interrupts sourced from the I2C Controllers 0 - 3.
0363      *  * All interrupts in this group are level triggered.
0364      */
0365
0366     ALT_INT_INTERRUPT_UART0 = 194, /*!< # */
0367     ALT_INT_INTERRUPT_UART1 = 195,
0368     /*!<
0369      * Interrupts sourced from the UARTs 0 - 1.
0370      *  * All interrupts in this group are level triggered.
0371      */
0372
0373     ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */
0374     ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */
0375     ALT_INT_INTERRUPT_GPIO2 = 198,
0376     /*!<
0377      * Interrupts sourced from the GPIO 0 - 2.
0378      *  * All interrupts in this group are level triggered.
0379      */
0380
0381     ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */
0382     ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */
0383     ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */
0384     ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202,
0385     /*!<
0386      * Interrupts sourced from the Timer controllers.
0387      *  * All interrupts in this group are level triggered.
0388      */
0389
0390     ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */
0391     ALT_INT_INTERRUPT_WDOG1_IRQ = 204,
0392     /*!<
0393      * Interrupts sourced from the Watchdog Timers 0 - 1.
0394      *  * All interrupts in this group are level triggered.
0395      */
0396
0397     ALT_INT_INTERRUPT_CLKMGR_IRQ = 205,
0398     /*!<
0399      * Interrupts sourced from the Clock Manager.
0400      *  * All interrupts in this group are level triggered.
0401      */
0402
0403     ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206,
0404     /*!<
0405      * Interrupts sourced from the Clock Manager MPU Wakeup.
0406      *  * All interrupts in this group are level triggered.
0407      */
0408
0409     ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207,
0410     /*!<
0411      * Interrupts sourced from the FPGA Manager.
0412      *  * All interrupts in this group are level triggered.
0413      */
0414
0415     ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */
0416     ALT_INT_INTERRUPT_NCTIIRQ1 = 209,
0417     /*!<
0418      * Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI.
0419      *  * All interrupts in this group are level triggered.
0420      */
0421
0422     ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ   = 210, /*!< # */
0423     ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211
0424     /*!<
0425      * Interrupts sourced from the On-chip RAM.
0426      *  * All interrupts in this group are level triggered.
0427      */
0428
0429 } ALT_INT_INTERRUPT_t;
0430
0431 /*!
0432  * This is the CPU target type. It is used to specify a set of CPUs on the
0433  * system. If only bit 0 is set then it specifies a set of CPUs containing
0434  * only CPU 0. Multiple CPUs can be specified by setting the appropriate bit
0435  * up to the number of CPUs on the system.
0436  */
0437 typedef uint32_t alt_int_cpu_target_t;
0438
0439 /*!
0440  * This type definition enumerates all the interrupt trigger types.
0441  */
0442 typedef enum ALT_INT_TRIGGER_e
0443 {
0444     /*!
0445      * Edge triggered interrupt. This applies to Private Peripheral Interrupts
0446      * (PPI) and Shared Peripheral Interrupts (SPI) only, with interrupt IDs
0447      * 16 - 1019.
0448      */
0449     ALT_INT_TRIGGER_EDGE,
0450
0451     /*!
0452      * Level triggered interrupt. This applies to Private Peripheral
0453      * Interrupts (PPI) and Shared Peripheral Interrupts (SPI) only, with
0454      * interrupt IDs 16 - 1019.
0455      */
0456     ALT_INT_TRIGGER_LEVEL,
0457
0458     /*!
0459      * Software triggered interrupt. This applies to Software Generated
0460      * Interrupts (SGI) only, with interrupt IDs 0 - 15.
0461      */
0462     ALT_INT_TRIGGER_SOFTWARE,
0463
0464     /*!
0465      * All triggering types except for those in the Shared Peripheral Interrupts
0466      * (SPI) F2S FPGA family interrupts can be determined by the system
0467      * automatically. In all functions which ask for the triggering type, the
0468      * ALT_INT_TRIGGER_AUTODETECT can be used to select the correct trigger
0469      * type for all non F2S interrupt types.
0470      */
0471     ALT_INT_TRIGGER_AUTODETECT,
0472
0473     /*!
0474      * The interrupt triggering information is not applicable. This is possibly
0475      * due to querying an invalid interrupt identifier.
0476      */
0477     ALT_INT_TRIGGER_NA
0478 }
0479 ALT_INT_TRIGGER_t;
0480
0481 /*!
0482  * This type definition enumerates all the target list filter options. This is
0483  * used by the trigger Software Generated Interrupt (SGI) feature to issue a
0484  * SGI to the specified processor(s) in the system. Depending on the target
0485  * list filter and the target list, interrupts can be routed to any
0486  * combinations of CPUs.
0487  */
0488 typedef enum ALT_INT_SGI_TARGET_e
0489 {
0490     /*!
0491      * This filter list uses the target list parameter to specify which CPUs
0492      * to send the interrupt to. If target list is 0, no interrupts are sent.
0493      */
0494     ALT_INT_SGI_TARGET_LIST,
0495
0496     /*!
0497      * This filter list sends the interrupt all CPUs except the current CPU.
0498      * The target list parameter is ignored.
0499      */
0500     ALT_INT_SGI_TARGET_ALL_EXCL_SENDER,
0501
0502     /*!
0503      * This filter list sends the interrupt to the current CPU only. The
0504      * target list parameter is ignored.
0505      */
0506     ALT_INT_SGI_TARGET_SENDER_ONLY
0507 }
0508 ALT_INT_SGI_TARGET_t;
0509
0510 /*!
0511  * Extracts the CPUID field from the ICCIAR register.
0512  */
0513 #define ALT_INT_ICCIAR_CPUID_GET(icciar)    ((icciar >> 10) & 0x7)
0514
0515 /*!
0516  * Extracts the ACKINTID field from the ICCIAR register.
0517  */
0518 #define ALT_INT_ICCIAR_ACKINTID_GET(icciar) (icciar & 0x3FF)
0519
0520 /*!
0521  * The callback to use when an interrupt needs to be serviced.
0522  *
0523  * \param       icciar          The Interrupt Controller CPU Interrupt
0524  *                              Acknowledgement Register value (ICCIAR) value
0525  *                              corresponding to the current interrupt.
0526  *
0527  * \param       context         The user provided context.
0528  */
0529 typedef void (*alt_int_callback_t)(uint32_t icciar, void * context);
0530
0531 /*!
0532  * @}
0533  */
0534
0535 #ifdef __cplusplus
0536 }
0537 #endif
0538
0539 #endif /* __ALT_INT_COMMON_H__ */