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0001 /** 0002 * @file 0003 * 0004 * @ingroup RTEMSBSPsARMCycVContrib 0005 */ 0006 0007 /****************************************************************************** 0008 * 0009 * Copyright 2013 Altera Corporation. All Rights Reserved. 0010 * 0011 * Redistribution and use in source and binary forms, with or without 0012 * modification, are permitted provided that the following conditions are met: 0013 * 0014 * 1. Redistributions of source code must retain the above copyright notice, 0015 * this list of conditions and the following disclaimer. 0016 * 0017 * 2. Redistributions in binary form must reproduce the above copyright notice, 0018 * this list of conditions and the following disclaimer in the documentation 0019 * and/or other materials provided with the distribution. 0020 * 0021 * 3. The name of the author may not be used to endorse or promote products 0022 * derived from this software without specific prior written permission. 0023 * 0024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR 0025 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 0026 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO 0027 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 0028 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 0029 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 0030 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 0031 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 0032 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 0033 * OF SUCH DAMAGE. 0034 * 0035 ******************************************************************************/ 0036 0037 #ifndef __ALT_DMA_PROGRAM_H__ 0038 #define __ALT_DMA_PROGRAM_H__ 0039 0040 #include "hwlib.h" 0041 #include "alt_dma_common.h" 0042 0043 #ifdef __cplusplus 0044 extern "C" 0045 { 0046 #endif /* __cplusplus */ 0047 0048 /*! 0049 * \addtogroup ALT_DMA_PRG DMA Controller Programming API 0050 * 0051 * This API provides functions for dynamically defining and assembling microcode 0052 * programs for execution on the DMA controller. 0053 * 0054 * The microcode program assembly API provides users with the ability to develop 0055 * highly optimized and tailored algorithms for data transfer between SoC FPGA 0056 * IP blocks and/or system memory. 0057 * 0058 * The same microcode program assembly facilities are also used to implement the 0059 * functions found in the HWLIB Common DMA Operations functional API. 0060 * 0061 * An ALT_DMA_PROGRAM_t structure is used to contain and assemble a DMA 0062 * microcode program. The storage for an ALT_DMA_PROGRAM_t stucture is allocated 0063 * from used specified system memory. Once a microcode program has been 0064 * assembled in a ALT_DMA_PROGRAM_t it may be excecuted on a designated DMA 0065 * channel thread. The microcode program may be rerun on any DMA channel thread 0066 * whenever required as long as the integrity of the ALT_DMA_PROGRAM_t 0067 * containing the program is maintained. 0068 * 0069 * @{ 0070 */ 0071 0072 /*! 0073 * This preprocessor declares the DMA channel thread microcode instruction 0074 * cache line width in bytes. It is recommended that the program buffers be 0075 * sized to a multiple of the cache line size. This will allow for the most 0076 * efficient microcode speed and space utilization. 0077 */ 0078 #define ALT_DMA_PROGRAM_CACHE_LINE_SIZE (32) 0079 0080 /*! 0081 * This preprocessor declares the DMA channel thread microcode instruction 0082 * cache line count. Thus the total size of the cache is the cache line size 0083 * multipled by the cache line count. Programs larger than the cache size risk 0084 * having a cache miss while executing. 0085 */ 0086 #define ALT_DMA_PROGRAM_CACHE_LINE_COUNT (16) 0087 0088 /*! 0089 * This preprocessor definition determines the size of the program buffer 0090 * within the ALT_DMA_PROGRAM_t structure. This size should provide adequate 0091 * size for most DMA microcode programs. If calls within this API are 0092 * reporting out of memory response codes, consider increasing the provisioned 0093 * program buffersize. 0094 * 0095 * To specify another DMA microcode program buffer size, redefine the macro 0096 * below by defining ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE to another size in 0097 * your Makefile. It is recommended that the size be a multiple of the 0098 * microcode engine cache line size. See ALT_DMA_PROGRAM_CACHE_LINE_SIZE for 0099 * more information. The largest supported buffer size is 65536 bytes. 0100 */ 0101 #ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE 0102 #define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT) 0103 #endif 0104 0105 /*! 0106 * This type defines the structure used to assemble and contain a microcode 0107 * program which can be executed by the DMA controller. The internal members 0108 * are undocumented and should not be altered outside of this API. 0109 */ 0110 typedef struct ALT_DMA_PROGRAM_s 0111 { 0112 uint32_t flag; 0113 0114 uint16_t buffer_start; 0115 uint16_t code_size; 0116 0117 uint16_t loop0; 0118 uint16_t loop1; 0119 0120 uint16_t sar; 0121 uint16_t dar; 0122 0123 /* 0124 * Add a little extra space so that regardless of where this structure 0125 * sits in memory, a suitable start address can be aligned to the cache 0126 * line stride while providing the requested buffer space. 0127 */ 0128 uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE + 0129 ALT_DMA_PROGRAM_CACHE_LINE_SIZE]; 0130 } 0131 ALT_DMA_PROGRAM_t; 0132 0133 /*! 0134 * This type definition enumerates the DMA controller register names for use in 0135 * microcode program definition. 0136 */ 0137 typedef enum ALT_DMA_PROGRAM_REG_e 0138 { 0139 /*! Source Address Register */ 0140 ALT_DMA_PROGRAM_REG_SAR = 0x0, 0141 0142 /*! Destination Address Register */ 0143 ALT_DMA_PROGRAM_REG_DAR = 0x2, 0144 0145 /*! Channel Control Register */ 0146 ALT_DMA_PROGRAM_REG_CCR = 0x1 0147 } 0148 ALT_DMA_PROGRAM_REG_t; 0149 0150 /*! 0151 * This type definition enumerates the instruction modifier options available 0152 * for use with selected DMA microcode instructions. 0153 * 0154 * The enumerations values are context dependent upon the instruction being 0155 * modified. 0156 * 0157 * For the <b>DMALD[S|B]</b>, <b>DMALDP\<S|B></b>, <b>DMAST[S|B]</b>, and 0158 * <b>DMASTP\<S|B></b> microcode instructions, the enumeration 0159 * ALT_DMA_PROGRAM_INST_MOD_SINGLE specifies the <b>S</b> option modifier 0160 * while the enumeration ALT_DMA_PROGRAM_INST_MOD_BURST specifies the <b>B</b> 0161 * option modifier. The enumeration ALT_DMA_PROGRAM_INST_MOD_NONE specifies 0162 * that no modifier is present for instructions where use of <b>[S|B]</b> is 0163 * optional. 0164 * 0165 * For the <b>DMAWFP</b> microcode instruction, the enumerations 0166 * ALT_DMA_PROGRAM_INST_MOD_SINGLE, ALT_DMA_PROGRAM_INST_MOD_BURST, or 0167 * ALT_DMA_PROGRAM_INST_MOD_PERIPH each specify one of the corresponding 0168 * options <b>\<single|burst|periph></b>. 0169 */ 0170 typedef enum ALT_DMA_PROGRAM_INST_MOD_e 0171 { 0172 /*! 0173 * This DMA instruction modifier specifies that no special modifier is 0174 * added to the instruction. 0175 */ 0176 ALT_DMA_PROGRAM_INST_MOD_NONE, 0177 0178 /*! 0179 * Depending on the DMA microcode instruction modified, this modifier 0180 * specifies <b>S</b> case for a <b>[S|B]</b> or a <b>\<single></b> for a 0181 * <b>\<single|burst|periph></b>. 0182 */ 0183 ALT_DMA_PROGRAM_INST_MOD_SINGLE, 0184 0185 /*! 0186 * Depending on the DMA microcode instruction modified, this modifier 0187 * specifies <b>B</b> case for a <b>[S|B]</b> or a <b>\<burst></b> for a 0188 * <b>\<single|burst|periph></b>. 0189 */ 0190 ALT_DMA_PROGRAM_INST_MOD_BURST, 0191 0192 /*! 0193 * This DMA instruction modifier specifies a <b>\<periph></b> for a 0194 * <b>\<single|burst|periph></b>. 0195 */ 0196 ALT_DMA_PROGRAM_INST_MOD_PERIPH 0197 } 0198 ALT_DMA_PROGRAM_INST_MOD_t; 0199 0200 /*! 0201 * This function initializes a system memory buffer for use as a DMA microcode 0202 * program buffer. This should be the first API call made on the program 0203 * buffer type. 0204 * 0205 * \param pgm 0206 * A pointer to a DMA program buffer structure. 0207 * 0208 * \retval ALT_E_SUCCESS The operation was successful. 0209 * \retval ALT_E_ERROR Details about error status code 0210 */ 0211 ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm); 0212 0213 /*! 0214 * This function verifies that the DMA microcode program buffer is no longer 0215 * in use and performs any needed uninitialization steps. 0216 * 0217 * \param pgm 0218 * A pointer to a DMA program buffer structure. 0219 * 0220 * \retval ALT_E_SUCCESS The operation was successful. 0221 * \retval ALT_E_ERROR Details about error status code 0222 */ 0223 ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm); 0224 0225 /*! 0226 * This function clears the existing DMA microcode program in the given 0227 * program buffer. 0228 * 0229 * \param pgm 0230 * A pointer to a DMA program buffer structure. 0231 * 0232 * \retval ALT_E_SUCCESS The operation was successful. 0233 * \retval ALT_E_ERROR Details about error status code. 0234 */ 0235 ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm); 0236 0237 /*! 0238 * This function validate that the given DMA microcode program buffer contains 0239 * a well formed program. If caches are enabled, the program buffer contents 0240 * will be cleaned to RAM. 0241 * 0242 * \param pgm 0243 * A pointer to a DMA program buffer structure. 0244 * 0245 * \retval ALT_E_SUCCESS The given program is well formed. 0246 * \retval ALT_E_ERROR The given program is not well formed. 0247 * \retval ALT_E_TMO The cache operation timed out. 0248 */ 0249 ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm); 0250 0251 /*! 0252 * This function reports the number bytes incremented for the register 0253 * specified. The purpose is to determine the progress of an ongoing DMA 0254 * transfer. 0255 * 0256 * It is implemented by calculating the difference of the programmed SAR or DAR 0257 * with the current channel SAR or DAR register value. 0258 * 0259 * \param pgm 0260 * A pointer to a DMA program buffer structure. 0261 * 0262 * \param channel 0263 * The channel that the program is running on. 0264 * 0265 * \param reg 0266 * Register to change the value for. Valid for only 0267 * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. 0268 * 0269 * \param current 0270 * The current snapshot value of the register read from the DMA 0271 * channel. 0272 * 0273 * \param progress 0274 * [out] A pointer to a memory location that will be used to store 0275 * the number of bytes transfered. 0276 * 0277 * \retval ALT_E_SUCCESS The operation was successful. 0278 * \retval ALT_E_ERROR Details about error status code. 0279 * \retval ALT_E_BAD_ARG The specified channel is invalid, the specified 0280 * register is invalid, or the DMAMOV for the 0281 * specified register has not yet been assembled 0282 * in the current program buffer. 0283 */ 0284 ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm, 0285 ALT_DMA_PROGRAM_REG_t reg, 0286 uint32_t current, uint32_t * progress); 0287 0288 /*! 0289 * This function updates a pre-existing DMAMOV value affecting the SAR or DAR 0290 * registers. This allows for pre-assembled programs that can be used on 0291 * different source and destination addresses. 0292 * 0293 * \param pgm 0294 * A pointer to a DMA program buffer structure. 0295 * 0296 * \param reg 0297 * Register to change the value for. Valid for only 0298 * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. 0299 * 0300 * \param val 0301 * The value to update to. 0302 * 0303 * \retval ALT_E_SUCCESS The operation was successful. 0304 * \retval ALT_E_ERROR Details about error status code. 0305 * \retval ALT_E_BAD_ARG The specified register is invalid or the DMAMOV 0306 * for the specified register has not yet been 0307 * assembled in the current program buffer. 0308 */ 0309 ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm, 0310 ALT_DMA_PROGRAM_REG_t reg, uint32_t val); 0311 0312 /*! 0313 */ 0314 0315 /*! 0316 * Assembles a DMAADDH (Add Halfword) instruction into the microcode program 0317 * buffer. This instruction uses 3 bytes of buffer space. 0318 * 0319 * \param pgm 0320 * The DMA program buffer to contain the assembled instruction. 0321 * 0322 * \param addr_reg 0323 * The channel address register (ALT_DMA_PROGRAM_REG_DAR or 0324 * ALT_DMA_PROGRAM_REG_SAR) to add the value to. 0325 * 0326 * \param val 0327 * The 16-bit unsigned value to add to the channel address 0328 * register. 0329 * 0330 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0331 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0332 * \retval ALT_E_BAD_ARG Invalid channel register specified. 0333 */ 0334 // Assembler Syntax: DMAADDH <address_register>, <16-bit immediate> 0335 ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm, 0336 ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); 0337 0338 /*! 0339 * Assembles a DMAADNH (Add Negative Halfword) instruction into the microcode 0340 * program buffer. This instruction uses 3 bytes of buffer space. 0341 * 0342 * \param pgm 0343 * The DMA programm buffer to contain the assembled instruction. 0344 * 0345 * \param addr_reg 0346 * The channel address register (ALT_DMA_PROGRAM_REG_DAR or 0347 * ALT_DMA_PROGRAM_REG_SAR) to add the value to. 0348 * 0349 * \param val 0350 * The 16-bit unsigned value to add to the channel address 0351 * register. 0352 * 0353 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0354 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0355 * \retval ALT_E_BAD_ARG Invalid channel register specified. 0356 */ 0357 // Assembler Syntax: DMAADNH <address_register>, <16-bit immediate> 0358 ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm, 0359 ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); 0360 0361 /*! 0362 * Assembles a DMAEND (End) instruction into the microcode program buffer. 0363 * This instruction uses 1 byte of buffer space. 0364 * 0365 * \param pgm 0366 * The DMA programm buffer to contain the assembled instruction. 0367 * 0368 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0369 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0370 */ 0371 // Assembler Syntax: DMAEND 0372 ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm); 0373 0374 /*! 0375 * Assembles a DMAFLUSHP (Flush Peripheral) instruction into the microcode 0376 * program buffer. This instruction uses 2 bytes of buffer space. 0377 * 0378 * \param pgm 0379 * The DMA programm buffer to contain the assembled instruction. 0380 * 0381 * \param periph 0382 * The peripheral to flush. 0383 * 0384 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0385 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0386 * \retval ALT_E_BAD_ARG Invalid peripheral specified. 0387 */ 0388 // Assembler Syntax: DMAFLUSHP <peripheral> 0389 ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm, 0390 ALT_DMA_PERIPH_t periph); 0391 0392 /*! 0393 * Assembles a DMAGO (Go) instruction into the microcode program buffer. This 0394 * instruction uses 6 bytes of buffer space. 0395 * 0396 * \param pgm 0397 * The DMA programm buffer to contain the assembled instruction. 0398 * 0399 * \param channel 0400 * The stopped channel to act upon. 0401 * 0402 * \param val 0403 * The value to write to the channel program counter register. 0404 * 0405 * \param sec 0406 * The security state for the operation. 0407 * 0408 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0409 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0410 * \retval ALT_E_BAD_ARG Invalid channel or security specified. 0411 */ 0412 // Assembler Syntax: DMAGO <channel_number>, <32-bit_immediate> [, ns] 0413 ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm, 0414 ALT_DMA_CHANNEL_t channel, uint32_t val, 0415 ALT_DMA_SECURITY_t sec); 0416 0417 /*! 0418 * Assembles a DMAKILL (Kill) instruction into the microcode program buffer. 0419 * This instruction uses 1 byte of buffer space. 0420 * 0421 * \param pgm 0422 * The DMA programm buffer to contain the assembled instruction. 0423 * 0424 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0425 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0426 */ 0427 // Assembler Syntax: DMAKILL 0428 ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm); 0429 0430 /*! 0431 * Assembles a DMALD (Load) instruction into the microcode program buffer. 0432 * This instruction uses 1 byte of buffer space. 0433 * 0434 * \param pgm 0435 * The DMA programm buffer to contain the assembled instruction. 0436 * 0437 * \param mod 0438 * The program instruction modifier for the type of transfer. 0439 * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and 0440 * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. 0441 * 0442 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0443 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0444 * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. 0445 */ 0446 // Assembler Syntax: DMALD[S|B] 0447 ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm, 0448 ALT_DMA_PROGRAM_INST_MOD_t mod); 0449 0450 /*! 0451 * Assembles a DMALDP (Load and notify Peripheral) instruction into the 0452 * microcode program buffer. This instruction uses 2 bytes of buffer space. 0453 * 0454 * \param pgm 0455 * The DMA programm buffer to contain the assembled instruction. 0456 * 0457 * \param mod 0458 * The program instruction modifier for the type of transfer. 0459 * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and 0460 * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. 0461 * 0462 * \param periph 0463 * The peripheral to notify. 0464 * 0465 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0466 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0467 * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral 0468 * specified. 0469 */ 0470 // Assembler Syntax: DMALDP<S|B> <peripheral> 0471 ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm, 0472 ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); 0473 0474 /*! 0475 * Assembles a DMALP (Loop) instruction into the microcode program buffer. 0476 * This instruction uses 2 bytes of buffer space. 0477 * 0478 * \param pgm 0479 * The DMA programm buffer to contain the assembled instruction. 0480 * 0481 * \param iterations 0482 * The number of iterations to run for. Valid values are 1 - 256. 0483 * 0484 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0485 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0486 * \retval ALT_E_BAD_ARG Invalid iterations specified. 0487 * \retval ALT_E_BAD_OPERATION All loop registers are in use. 0488 */ 0489 // Assembler Syntax: DMALP [<LC0>|<LC1>] <loop_iterations> 0490 ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm, 0491 uint32_t iterations); 0492 0493 /*! 0494 * Assembles a DMALPEND (Loop End) instruction into the microcode program 0495 * buffer. This instruction uses 2 bytes of buffer space. 0496 * 0497 * \param pgm 0498 * The DMA programm buffer to contain the assembled instruction. 0499 * 0500 * \param mod 0501 * The program instruction modifier for the loop terminator. Only 0502 * ALT_DMA_PROGRAM_INST_MOD_NONE, ALT_DMA_PROGRAM_INST_MOD_SINGLE 0503 * and ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. 0504 * 0505 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0506 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0507 * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. 0508 * \retval ALT_E_ARG_RANGE Loop size is too large to be supported. 0509 * \retval ALT_E_BAD_OPERATION A valid DMALP or DMALPFE was not added to 0510 * the program buffer before adding this 0511 * DMALPEND instruction. 0512 */ 0513 // Assembler Syntax: DMALPEND[S|B] 0514 ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm, 0515 ALT_DMA_PROGRAM_INST_MOD_t mod); 0516 0517 /*! 0518 * Assembles a DMALPFE (Loop Forever) instruction into the microcode program 0519 * buffer. No instruction is added to the buffer but a previous DMALPEND to 0520 * create an infinite loop. 0521 * 0522 * \param pgm 0523 * The DMA programm buffer to contain the assembled instruction. 0524 * 0525 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0526 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0527 */ 0528 // Assembler Syntax: DMALPFE 0529 ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm); 0530 0531 /*! 0532 * Assembles a DMAMOV (Move) instruction into the microcode program buffer. 0533 * This instruction uses 6 bytes of buffer space. 0534 * 0535 * \param pgm 0536 * The DMA programm buffer to contain the assembled instruction. 0537 * 0538 * \param chan_reg 0539 * The channel non-looping register (ALT_DMA_PROGRAM_REG_SAR, 0540 * ALT_DMA_PROGRAM_REG_DAR or ALT_DMA_PROGRAM_REG_CCR) to copy 0541 * the value to. 0542 * 0543 * \param val 0544 * The value to write to the specified register. 0545 * 0546 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0547 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0548 * \retval ALT_E_BAD_ARG Invalid channel register specified. 0549 */ 0550 // Assembler Syntax: DMAMOV <destination_register>, <32-bit_immediate> 0551 ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm, 0552 ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val); 0553 0554 /*! 0555 * Assembles a DMANOP (No Operation) instruction into the microcode program 0556 * buffer. This instruction uses 1 byte of buffer space. 0557 * 0558 * \param pgm 0559 * The DMA programm buffer to contain the assembled instruction. 0560 * 0561 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0562 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0563 */ 0564 // Assembler Syntax: DMANOP 0565 ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm); 0566 0567 /*! 0568 * Assembles a DMARMB (Read Memory Barrier) instruction into the microcode 0569 * program buffer. This instruction uses 1 byte of buffer space. 0570 * 0571 * \param pgm 0572 * The DMA programm buffer to contain the assembled instruction. 0573 * 0574 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0575 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0576 */ 0577 // Assembler Syntax: DMARMB 0578 ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm); 0579 0580 /*! 0581 * Assembles a DMASEV (Send Event) instruction into the microcode program 0582 * buffer. This instruction uses 2 byte of buffer space. 0583 * 0584 * \param pgm 0585 * The DMA programm buffer to contain the assembled instruction. 0586 * 0587 * \param evt 0588 * The event to send. 0589 * 0590 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0591 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0592 * \retval ALT_E_BAD_ARG Invalid event specified. 0593 */ 0594 // Assembler Syntax: DMASEV <event_num> 0595 ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm, 0596 ALT_DMA_EVENT_t evt); 0597 0598 /*! 0599 * Assembles a DMAST (Store) instruction into the microcode program buffer. 0600 * This instruction uses 1 byte of buffer space. 0601 * 0602 * \param pgm 0603 * The DMA programm buffer to contain the assembled instruction. 0604 * 0605 * \param mod 0606 * The program instruction modifier for the type of transfer. 0607 * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and 0608 * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. 0609 * 0610 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0611 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0612 */ 0613 // Assembler Syntax: DMAST[S|B] 0614 ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm, 0615 ALT_DMA_PROGRAM_INST_MOD_t mod); 0616 0617 /*! 0618 * Assembles a DMASTP (Store and notify Peripheral) instruction into the 0619 * microcode program buffer. This instruction uses 2 bytes of buffer space. 0620 * 0621 * \param pgm 0622 * The DMA programm buffer to contain the assembled instruction. 0623 * 0624 * \param mod 0625 * The program instruction modifier for the type of transfer. 0626 * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and 0627 * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. 0628 * 0629 * \param periph 0630 * The peripheral to notify. 0631 * 0632 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0633 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0634 * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral 0635 * specified. 0636 */ 0637 // Assembler Syntax: DMASTP<S|B> <peripheral> 0638 ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm, 0639 ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); 0640 0641 /*! 0642 * Assembles a DMASTZ (Store Zero) instruction into the microcode program 0643 * buffer. This instruction uses 1 byte of buffer space. 0644 * 0645 * \param pgm 0646 * The DMA programm buffer to contain the assembled instruction. 0647 * 0648 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0649 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0650 */ 0651 // Assembler Syntax: DMASTZ 0652 ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm); 0653 0654 /*! 0655 * Assembles a DMAWFE (Wait For Event) instruction into the microcode program 0656 * buffer. This instruction uses 2 byte of buffer space. 0657 * 0658 * \param pgm 0659 * The DMA programm buffer to contain the assembled instruction. 0660 * 0661 * \param evt 0662 * The event to wait for. 0663 * 0664 * \param invalid 0665 * If invalid is set to true, the instruction will be configured 0666 * to invalidate the instruction cache for the current DMA 0667 * thread. 0668 * 0669 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0670 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0671 * \retval ALT_E_BAD_ARG Invalid event specified. 0672 */ 0673 // Assembler Syntax: DMAWFE <event_num>[, invalid] 0674 ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm, 0675 ALT_DMA_EVENT_t evt, bool invalid); 0676 0677 /*! 0678 * Assembles a DMAWFP (Wait for Peripheral) instruction into the microcode 0679 * program buffer. This instruction uses 2 bytes of buffer space. 0680 * 0681 * \param pgm 0682 * The DMA programm buffer to contain the assembled instruction. 0683 * 0684 * \param periph 0685 * The peripheral to wait on. 0686 * 0687 * \param mod 0688 * The program instruction modifier for the type of transfer. 0689 * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE, 0690 * ALT_DMA_PROGRAM_INST_MOD_BURST, or 0691 * ALT_DMA_PROGRAM_INST_MOD_PERIPH are valid options. 0692 * 0693 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0694 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0695 * \retval ALT_E_BAD_ARG Invalid peripheral or instruction modifier 0696 * specified. 0697 */ 0698 // Assembler Syntax: DMAWFP <peripheral>, <single|burst|periph> 0699 ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm, 0700 ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod); 0701 0702 /*! 0703 * Assembles a DMAWMB (Write Memory Barrier) instruction into the microcode 0704 * program buffer. This instruction uses 1 byte of buffer space. 0705 * 0706 * \param pgm 0707 * The DMA programm buffer to contain the assembled instruction. 0708 * 0709 * \retval ALT_E_SUCCESS Successful instruction assembly status. 0710 * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. 0711 */ 0712 // Assembler Syntax: DMAWMB 0713 ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm); 0714 0715 /*! 0716 * \addtogroup DMA_CCR Support for DMAMOV CCR 0717 * 0718 * The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the 0719 * dynamic microcode programming of the assembler directive: 0720 \verbatim 0721 0722 DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA<I|F>] 0723 [SP<imm3>] [SC<imm4>] 0724 [DB<1-16>] [DS<8|16|32|64|128>] [DA<I|F>] 0725 [DP<imm3>] [DC<imm4>] 0726 [ES<8|16|32|64|128>] 0727 0728 \endverbatim 0729 * with a DMAMOV instruction (see: alt_dma_program_DMAMOV()). 0730 * 0731 * For example the assembler directive: 0732 \verbatim 0733 DMAMOV CCR SB1 SS32 DB1 DS32 0734 \endverbatim 0735 * would be dynamically programmed with the following API call: 0736 \verbatim 0737 alt_dma_program_DMAMOV( pgm, 0738 ALT_DMA_PROGRAM_REG_CCR, 0739 ( ALT_DMA_CCR_OPT_SB1 0740 | ALT_DMA_CCR_OPT_SS32 0741 | ALT_DMA_CCR_OPT_SA_DEFAULT 0742 | ALT_DMA_CCR_OPT_SP_DEFAULT 0743 | ALT_DMA_CCR_OPT_SC_DEFAULT 0744 | ALT_DMA_CCR_OPT_DB1 0745 | ALT_DMA_CCR_OPT_DS32 0746 | ALT_DMA_CCR_OPT_DA_DEFAULT 0747 | ALT_DMA_CCR_OPT_DP_DEFAULT 0748 | ALT_DMA_CCR_OPT_DC_DEFAULT 0749 | ALT_DMA_CCR_OPT_ES8 0750 ) 0751 ); 0752 \endverbatim 0753 * 0754 * Each CCR option category should be specified regardless of whether it 0755 * specifies a custom value or the normal default value (i.e. an 0756 * ALT_DMA_CCR_OPT_*_DEFAULT. 0757 * 0758 * @{ 0759 */ 0760 0761 /* 0762 * Source Address {Fixed,Incrementing} 0763 */ 0764 /*! Source Address Fixed address burst. */ 0765 #define ALT_DMA_CCR_OPT_SAF (0 << 0) 0766 /*! Source Address Incrementing address burst. */ 0767 #define ALT_DMA_CCR_OPT_SAI (1 << 0) 0768 /*! Source Address Default value. */ 0769 #define ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI 0770 0771 /* 0772 * Source burst Size (in bits) 0773 */ 0774 /*! Source burst Size of 8 bits. */ 0775 #define ALT_DMA_CCR_OPT_SS8 (0 << 1) 0776 /*! Source burst Size of 16 bits. */ 0777 #define ALT_DMA_CCR_OPT_SS16 (1 << 1) 0778 /*! Source burst Size of 32 bits. */ 0779 #define ALT_DMA_CCR_OPT_SS32 (2 << 1) 0780 /*! Source burst Size of 64 bits. */ 0781 #define ALT_DMA_CCR_OPT_SS64 (3 << 1) 0782 /*! Source burst Size of 128 bits. */ 0783 #define ALT_DMA_CCR_OPT_SS128 (4 << 1) 0784 /*! Source burst Size default bits. */ 0785 #define ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8 0786 0787 /* 0788 * Source burst Length (in transfer(s)) 0789 */ 0790 /*! Source Burst length of 1 transfer. */ 0791 #define ALT_DMA_CCR_OPT_SB1 (0x0 << 4) 0792 /*! Source Burst length of 2 transfers. */ 0793 #define ALT_DMA_CCR_OPT_SB2 (0x1 << 4) 0794 /*! Source Burst length of 3 transfers. */ 0795 #define ALT_DMA_CCR_OPT_SB3 (0x2 << 4) 0796 /*! Source Burst length of 4 transfers. */ 0797 #define ALT_DMA_CCR_OPT_SB4 (0x3 << 4) 0798 /*! Source Burst length of 5 transfers. */ 0799 #define ALT_DMA_CCR_OPT_SB5 (0x4 << 4) 0800 /*! Source Burst length of 6 transfers. */ 0801 #define ALT_DMA_CCR_OPT_SB6 (0x5 << 4) 0802 /*! Source Burst length of 7 transfers. */ 0803 #define ALT_DMA_CCR_OPT_SB7 (0x6 << 4) 0804 /*! Source Burst length of 8 transfers. */ 0805 #define ALT_DMA_CCR_OPT_SB8 (0x7 << 4) 0806 /*! Source Burst length of 9 transfers. */ 0807 #define ALT_DMA_CCR_OPT_SB9 (0x8 << 4) 0808 /*! Source Burst length of 10 transfers. */ 0809 #define ALT_DMA_CCR_OPT_SB10 (0x9 << 4) 0810 /*! Source Burst length of 11 transfers. */ 0811 #define ALT_DMA_CCR_OPT_SB11 (0xa << 4) 0812 /*! Source Burst length of 12 transfers. */ 0813 #define ALT_DMA_CCR_OPT_SB12 (0xb << 4) 0814 /*! Source Burst length of 13 transfers. */ 0815 #define ALT_DMA_CCR_OPT_SB13 (0xc << 4) 0816 /*! Source Burst length of 14 transfers. */ 0817 #define ALT_DMA_CCR_OPT_SB14 (0xd << 4) 0818 /*! Source Burst length of 15 transfers. */ 0819 #define ALT_DMA_CCR_OPT_SB15 (0xe << 4) 0820 /*! Source Burst length of 16 transfers. */ 0821 #define ALT_DMA_CCR_OPT_SB16 (0xf << 4) 0822 /*! Source Burst length default transfers. */ 0823 #define ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1 0824 0825 /* 0826 * Source Protection 0827 */ 0828 /*! Source Protection bits for AXI bus ARPROT[2:0]. */ 0829 #define ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8) 0830 /*! Source Protection bits default value. */ 0831 #define ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0) 0832 0833 /* 0834 * Source cache 0835 */ 0836 /*! Source Cache bits for AXI bus ARCACHE[2:0]. */ 0837 #define ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11) 0838 /*! Source Cache bits default value. */ 0839 #define ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0) 0840 0841 /* 0842 * Destination Address {Fixed,Incrementing} 0843 */ 0844 /*! Destination Address Fixed address burst. */ 0845 #define ALT_DMA_CCR_OPT_DAF (0 << 14) 0846 /*! Destination Address Incrementing address burst. */ 0847 #define ALT_DMA_CCR_OPT_DAI (1 << 14) 0848 /*! Destination Address Default value. */ 0849 #define ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI 0850 0851 /* 0852 * Destination burst Size (in bits) 0853 */ 0854 /*! Destination burst Size of 8 bits. */ 0855 #define ALT_DMA_CCR_OPT_DS8 (0 << 15) 0856 /*! Destination burst Size of 16 bits. */ 0857 #define ALT_DMA_CCR_OPT_DS16 (1 << 15) 0858 /*! Destination burst Size of 32 bits. */ 0859 #define ALT_DMA_CCR_OPT_DS32 (2 << 15) 0860 /*! Destination burst Size of 64 bits. */ 0861 #define ALT_DMA_CCR_OPT_DS64 (3 << 15) 0862 /*! Destination burst Size of 128 bits. */ 0863 #define ALT_DMA_CCR_OPT_DS128 (4 << 15) 0864 /*! Destination burst Size default bits. */ 0865 #define ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8 0866 0867 /* 0868 * Destination Burst length (in transfer(s)) 0869 */ 0870 /*! Destination Burst length of 1 transfer. */ 0871 #define ALT_DMA_CCR_OPT_DB1 (0x0 << 18) 0872 /*! Destination Burst length of 2 transfers. */ 0873 #define ALT_DMA_CCR_OPT_DB2 (0x1 << 18) 0874 /*! Destination Burst length of 3 transfers. */ 0875 #define ALT_DMA_CCR_OPT_DB3 (0x2 << 18) 0876 /*! Destination Burst length of 4 transfers. */ 0877 #define ALT_DMA_CCR_OPT_DB4 (0x3 << 18) 0878 /*! Destination Burst length of 5 transfers. */ 0879 #define ALT_DMA_CCR_OPT_DB5 (0x4 << 18) 0880 /*! Destination Burst length of 6 transfers. */ 0881 #define ALT_DMA_CCR_OPT_DB6 (0x5 << 18) 0882 /*! Destination Burst length of 7 transfers. */ 0883 #define ALT_DMA_CCR_OPT_DB7 (0x6 << 18) 0884 /*! Destination Burst length of 8 transfers. */ 0885 #define ALT_DMA_CCR_OPT_DB8 (0x7 << 18) 0886 /*! Destination Burst length of 9 transfers. */ 0887 #define ALT_DMA_CCR_OPT_DB9 (0x8 << 18) 0888 /*! Destination Burst length of 10 transfers. */ 0889 #define ALT_DMA_CCR_OPT_DB10 (0x9 << 18) 0890 /*! Destination Burst length of 11 transfers. */ 0891 #define ALT_DMA_CCR_OPT_DB11 (0xa << 18) 0892 /*! Destination Burst length of 12 transfers. */ 0893 #define ALT_DMA_CCR_OPT_DB12 (0xb << 18) 0894 /*! Destination Burst length of 13 transfers. */ 0895 #define ALT_DMA_CCR_OPT_DB13 (0xc << 18) 0896 /*! Destination Burst length of 14 transfers. */ 0897 #define ALT_DMA_CCR_OPT_DB14 (0xd << 18) 0898 /*! Destination Burst length of 15 transfers. */ 0899 #define ALT_DMA_CCR_OPT_DB15 (0xe << 18) 0900 /*! Destination Burst length of 16 transfers. */ 0901 #define ALT_DMA_CCR_OPT_DB16 (0xf << 18) 0902 /*! Destination Burst length default transfers. */ 0903 #define ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1 0904 0905 /* 0906 * Destination Protection 0907 */ 0908 /*! Destination Protection bits for AXI bus AWPROT[2:0]. */ 0909 #define ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22) 0910 /*! Destination Protection bits default value. */ 0911 #define ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0) 0912 0913 /* 0914 * Destination Cache 0915 */ 0916 /*! Destination Cache bits for AXI bus AWCACHE[3,1:0]. */ 0917 #define ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25) 0918 /*! Destination Cache bits default value. */ 0919 #define ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0) 0920 0921 /* 0922 * Endian Swap size (in bits) 0923 */ 0924 /*! Endian Swap: No swap, 8-bit data. */ 0925 #define ALT_DMA_CCR_OPT_ES8 (0 << 28) 0926 /*! Endian Swap: Swap bytes within 16-bit data. */ 0927 #define ALT_DMA_CCR_OPT_ES16 (1 << 28) 0928 /*! Endian Swap: Swap bytes within 32-bit data. */ 0929 #define ALT_DMA_CCR_OPT_ES32 (2 << 28) 0930 /*! Endian Swap: Swap bytes within 64-bit data. */ 0931 #define ALT_DMA_CCR_OPT_ES64 (3 << 28) 0932 /*! Endian Swap: Swap bytes within 128-bit data. */ 0933 #define ALT_DMA_CCR_OPT_ES128 (4 << 28) 0934 /*! Endian Swap: Default byte swap. */ 0935 #define ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8 0936 0937 /*! Default CCR register options for a DMAMOV CCR assembler directive. */ 0938 #define ALT_DMA_CCR_OPT_DEFAULT \ 0939 (ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \ 0940 ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \ 0941 ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \ 0942 ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \ 0943 ALT_DMA_CCR_OPT_ES8) 0944 0945 /*! 0946 * @} 0947 */ 0948 0949 /*! 0950 * @} 0951 */ 0952 0953 #ifdef __cplusplus 0954 } 0955 #endif /* __cplusplus */ 0956 0957 #endif /* __ALT_DMA_PROGRAM_H__ */
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