include/bsp/alt_dma_common.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMCycVContrib
0005  */
0006
0007 /******************************************************************************
0008  *
0009  * Copyright 2013 Altera Corporation. All Rights Reserved.
0010  *
0011  * Redistribution and use in source and binary forms, with or without
0012  * modification, are permitted provided that the following conditions are met:
0013  *
0014  * 1. Redistributions of source code must retain the above copyright notice,
0015  * this list of conditions and the following disclaimer.
0016  *
0017  * 2. Redistributions in binary form must reproduce the above copyright notice,
0018  * this list of conditions and the following disclaimer in the documentation
0019  * and/or other materials provided with the distribution.
0020  *
0021  * 3. The name of the author may not be used to endorse or promote products
0022  * derived from this software without specific prior written permission.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
0025  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0026  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
0027  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0028  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
0029  * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0032  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
0033  * OF SUCH DAMAGE.
0034  *
0035  ******************************************************************************/
0036
0037 #ifndef __ALT_DMA_COMMON_H__
0038 #define __ALT_DMA_COMMON_H__
0039
0040 #ifdef __cplusplus
0041 extern "C"
0042 {
0043 #endif  /* __cplusplus */
0044
0045 /*!
0046  * \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions
0047  *
0048  * This module contains the common definitions for the DMA controller related
0049  * APIs.
0050  *
0051  * @{
0052  */
0053
0054 /*!
0055  * This type definition enumerates the DMA controller channel threads.
0056  */
0057 typedef enum ALT_DMA_CHANNEL_e
0058 {
0059     ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */
0060     ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */
0061     ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */
0062     ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */
0063     ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */
0064     ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */
0065     ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */
0066     ALT_DMA_CHANNEL_7 = 7  /*!< DMA Channel Thread 7 */
0067 }
0068 ALT_DMA_CHANNEL_t;
0069
0070 /*!
0071  * This type definition enumerates the SoC system peripherals implementing the
0072  * required request interface that enables direct DMA transfers to/from the
0073  * device.
0074  *
0075  * FPGA soft IP interface to the DMA are required to comply with the Synopsys
0076  * protocol.
0077  *
0078  * Request interface numbers 4 through 7 are multiplexed between the CAN
0079  * controllers and soft logic implemented in the FPGA fabric. The selection
0080  * between the CAN controller and FPGA interfaces is determined at DMA
0081  * initialization.
0082  */
0083 typedef enum ALT_DMA_PERIPH_e
0084 {
0085     ALT_DMA_PERIPH_FPGA_0             = 0,  /*!< FPGA soft IP interface 0 */
0086     ALT_DMA_PERIPH_FPGA_1             = 1,  /*!< FPGA soft IP interface 1 */
0087     ALT_DMA_PERIPH_FPGA_2             = 2,  /*!< FPGA soft IP interface 2 */
0088     ALT_DMA_PERIPH_FPGA_3             = 3,  /*!< FPGA soft IP interface 3 */
0089
0090     ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4,  /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */
0091     ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5,  /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */
0092     ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6,  /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */
0093     ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7,  /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */
0094
0095     ALT_DMA_PERIPH_FPGA_4             = 4,  /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
0096     ALT_DMA_PERIPH_FPGA_5             = 5,  /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
0097     ALT_DMA_PERIPH_FPGA_6             = 6,  /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
0098     ALT_DMA_PERIPH_FPGA_7             = 7,  /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
0099
0100     ALT_DMA_PERIPH_CAN0_IF1           = 4,  /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
0101     ALT_DMA_PERIPH_CAN0_IF2           = 5,  /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
0102     ALT_DMA_PERIPH_CAN1_IF1           = 6,  /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
0103     ALT_DMA_PERIPH_CAN1_IF2           = 7,  /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
0104
0105     ALT_DMA_PERIPH_I2C0_TX            = 8,  /*!< I<sup>2</sup>C 0 TX */
0106     ALT_DMA_PERIPH_I2C0_RX            = 9,  /*!< I<sup>2</sup>C 0 RX */
0107     ALT_DMA_PERIPH_I2C1_TX            = 10, /*!< I<sup>2</sup>C 1 TX */
0108     ALT_DMA_PERIPH_I2C1_RX            = 11, /*!< I<sup>2</sup>C 1 RX */
0109     ALT_DMA_PERIPH_I2C2_TX            = 12, /*!< I<sup>2</sup>C 2 TX */
0110     ALT_DMA_PERIPH_I2C2_RX            = 13, /*!< I<sup>2</sup>C 2 RX */
0111     ALT_DMA_PERIPH_I2C3_TX            = 14, /*!< I<sup>2</sup>C 3 TX */
0112     ALT_DMA_PERIPH_I2C3_RX            = 15, /*!< I<sup>2</sup>C 3 RX */
0113     ALT_DMA_PERIPH_SPI0_MASTER_TX     = 16, /*!< SPI 0 Master TX */
0114     ALT_DMA_PERIPH_SPI0_MASTER_RX     = 17, /*!< SPI 0 Master RX */
0115     ALT_DMA_PERIPH_SPI0_SLAVE_TX      = 18, /*!< SPI 0 Slave TX */
0116     ALT_DMA_PERIPH_SPI0_SLAVE_RX      = 19, /*!< SPI 0 Slave RX */
0117     ALT_DMA_PERIPH_SPI1_MASTER_TX     = 20, /*!< SPI 1 Master TX */
0118     ALT_DMA_PERIPH_SPI1_MASTER_RX     = 21, /*!< SPI 1 Master RX */
0119     ALT_DMA_PERIPH_SPI1_SLAVE_TX      = 22, /*!< SPI 1 Slave TX */
0120     ALT_DMA_PERIPH_SPI1_SLAVE_RX      = 23, /*!< SPI 1 Slave RX */
0121     ALT_DMA_PERIPH_QSPI_FLASH_TX      = 24, /*!< QSPI Flash TX */
0122     ALT_DMA_PERIPH_QSPI_FLASH_RX      = 25, /*!< QSPI Flash RX */
0123     ALT_DMA_PERIPH_STM                = 26, /*!< System Trace Macrocell */
0124     ALT_DMA_PERIPH_RESERVED           = 27, /*!< Reserved */
0125     ALT_DMA_PERIPH_UART0_TX           = 28, /*!< UART 0 TX */
0126     ALT_DMA_PERIPH_UART0_RX           = 29, /*!< UART 0 RX */
0127     ALT_DMA_PERIPH_UART1_TX           = 30, /*!< UART 1 TX */
0128     ALT_DMA_PERIPH_UART1_RX           = 31  /*!< UART 1 RX */
0129 }
0130 ALT_DMA_PERIPH_t;
0131
0132 /*!
0133  * This type enumerates the DMA security state options available.
0134  */
0135 typedef enum ALT_DMA_SECURITY_e
0136 {
0137     ALT_DMA_SECURITY_DEFAULT   = 0, /*!< Use the default security value (e.g. reset default) */
0138     ALT_DMA_SECURITY_SECURE    = 1, /*!< Secure */
0139     ALT_DMA_SECURITY_NONSECURE = 2  /*!< Non-secure */
0140 }
0141 ALT_DMA_SECURITY_t;
0142
0143 /*!
0144  * This type definition enumerates the DMA event-interrupt resources.
0145  */
0146 typedef enum ALT_DMA_EVENT_e
0147 {
0148     ALT_DMA_EVENT_0     = 0, /*!< DMA Event 0 */
0149     ALT_DMA_EVENT_1     = 1, /*!< DMA Event 1 */
0150     ALT_DMA_EVENT_2     = 2, /*!< DMA Event 2 */
0151     ALT_DMA_EVENT_3     = 3, /*!< DMA Event 3 */
0152     ALT_DMA_EVENT_4     = 4, /*!< DMA Event 4 */
0153     ALT_DMA_EVENT_5     = 5, /*!< DMA Event 5 */
0154     ALT_DMA_EVENT_6     = 6, /*!< DMA Event 6 */
0155     ALT_DMA_EVENT_7     = 7, /*!< DMA Event 7 */
0156     ALT_DMA_EVENT_ABORT = 8  /*!< DMA Abort Event */
0157 }
0158 ALT_DMA_EVENT_t;
0159
0160 /*!
0161  * @}
0162  */
0163
0164 #ifdef __cplusplus
0165 }
0166 #endif /* __cplusplus */
0167
0168 #endif /* __ALT_DMA_COMMON_H__ */