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0001 /** 0002 * @file 0003 * 0004 * @ingroup RTEMSBSPsARMCycVContrib 0005 */ 0006 0007 /*! \file 0008 * Contains definitions for the Altera Hardware Libraries Clock Manager 0009 * Application Programming Interface 0010 */ 0011 0012 /****************************************************************************** 0013 * 0014 * Copyright 2013 Altera Corporation. All Rights Reserved. 0015 * 0016 * Redistribution and use in source and binary forms, with or without 0017 * modification, are permitted provided that the following conditions are met: 0018 * 0019 * 1. Redistributions of source code must retain the above copyright notice, 0020 * this list of conditions and the following disclaimer. 0021 * 0022 * 2. Redistributions in binary form must reproduce the above copyright notice, 0023 * this list of conditions and the following disclaimer in the documentation 0024 * and/or other materials provided with the distribution. 0025 * 0026 * 3. The name of the author may not be used to endorse or promote products 0027 * derived from this software without specific prior written permission. 0028 * 0029 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR 0030 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 0031 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO 0032 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 0033 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 0034 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 0035 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 0036 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 0037 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 0038 * OF SUCH DAMAGE. 0039 * 0040 ******************************************************************************/ 0041 0042 #ifndef __ALT_CLK_MGR_H__ 0043 #define __ALT_CLK_MGR_H__ 0044 0045 #include "hwlib.h" 0046 #include "alt_clock_group.h" 0047 0048 #ifdef __cplusplus 0049 extern "C" 0050 { 0051 #endif /* __cplusplus */ 0052 0053 /*! \addtogroup CLK_MGR The Clock Manager API 0054 * 0055 * This module defines the Clock Manager API for accessing, configuring, and 0056 * controlling the HPS clock resources. 0057 * 0058 * @{ 0059 */ 0060 0061 /******************************************************************************/ 0062 /*! 0063 * This type definition is an opaque type definition for clock frequency values 0064 * in Hz. 0065 */ 0066 typedef uint32_t alt_freq_t; 0067 0068 /******************************************************************************/ 0069 /*! 0070 * This type definition enumerates the names of the clock and PLL resources 0071 * managed by the Clock Manager. 0072 */ 0073 typedef enum ALT_CLK_e 0074 { 0075 /* Clock Input Pins */ 0076 ALT_CLK_IN_PIN_OSC1, 0077 /*!< \b OSC_CLK_1_HPS 0078 * External oscillator input: 0079 * * Input Pin 0080 * * Clock source to Main PLL 0081 * * Clock source to SDRAM PLL 0082 * and Peripheral PLL if selected via 0083 * register write 0084 * * Clock source for clock in safe mode 0085 */ 0086 0087 ALT_CLK_IN_PIN_OSC2, 0088 /*!< \b OSC_CLK_2_HPS 0089 * External Oscillator input: 0090 * * Input Pin 0091 * * Optional clock source to SDRAM PLL 0092 * and Peripheral PLL if selected 0093 * * Typically used for Ethernet 0094 * reference clock 0095 */ 0096 0097 0098 /* FPGA Clock Sources External to HPS */ 0099 ALT_CLK_F2H_PERIPH_REF, 0100 /*<! Alternate clock source from FPGA 0101 * for HPS Peripheral PLL. */ 0102 0103 ALT_CLK_F2H_SDRAM_REF, 0104 /*<! Alternate clock source from FPGA 0105 * for HPS SDRAM PLL. */ 0106 0107 0108 /* Other Clock Sources External to HPS */ 0109 ALT_CLK_IN_PIN_JTAG, 0110 /*!< \b JTAG_TCK_HPS 0111 * * Input Pin 0112 * * External HPS JTAG clock input. 0113 */ 0114 0115 ALT_CLK_IN_PIN_ULPI0, 0116 /*!< \b ULPI0_CLK 0117 * ULPI Clock provided by external USB0 0118 * PHY 0119 * * Input Pin 0120 */ 0121 0122 ALT_CLK_IN_PIN_ULPI1, 0123 /*!< \b ULPI1_CLK 0124 * ULPI Clock provided by external USB1 0125 * PHY 0126 * * Input Pin 0127 */ 0128 0129 ALT_CLK_IN_PIN_EMAC0_RX, 0130 /*!< \b EMAC0:RX_CLK 0131 * Rx Reference Clock for EMAC0 0132 * * Input Pin 0133 */ 0134 0135 ALT_CLK_IN_PIN_EMAC1_RX, 0136 /*!< \b EMAC1:RX_CLK 0137 * Rx Reference Clock for EMAC1 0138 * * Input Pin 0139 */ 0140 0141 0142 /* PLLs */ 0143 ALT_CLK_MAIN_PLL, 0144 /*!< \b main_pll_ref_clkin 0145 * Main PLL input reference clock, 0146 * used to designate the Main PLL in 0147 * PLL clock selections. 0148 */ 0149 0150 ALT_CLK_PERIPHERAL_PLL, 0151 /*!< \b periph_pll_ref_clkin 0152 * Peripheral PLL input reference 0153 * clock, used to designate the 0154 * Peripheral PLL in PLL clock 0155 * selections. 0156 */ 0157 0158 ALT_CLK_SDRAM_PLL, 0159 /*!< \b sdram_pll_ref_clkin 0160 * SDRAM PLL input reference clock, 0161 * used to designate the SDRAM PLL in 0162 * PLL clock selections. 0163 */ 0164 0165 /* OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived 0166 * directly from the osc_clk_1_HPS pin */ 0167 ALT_CLK_OSC1, 0168 /*!< \b osc1_clk 0169 * OSC1 Clock Group - The 0170 * OSC1 clock group contains 0171 * those clocks which are 0172 * derived directly from the 0173 * osc_clk_1_HPS pin. 0174 * * alias for ALT_CLK_IN_PIN_OSC1 0175 */ 0176 0177 /* Main Clock Group - The following clocks are derived from the Main PLL. */ 0178 ALT_CLK_MAIN_PLL_C0, 0179 /*!< \b Main PLL C0 Output */ 0180 0181 ALT_CLK_MAIN_PLL_C1, 0182 /*!< \b Main PLL C1 Output */ 0183 0184 ALT_CLK_MAIN_PLL_C2, 0185 /*!< \b Main PLL C2 Output */ 0186 0187 ALT_CLK_MAIN_PLL_C3, 0188 /*!< \b Main PLL C3 Output */ 0189 0190 ALT_CLK_MAIN_PLL_C4, 0191 /*!< \b Main PLL C4 Output */ 0192 0193 ALT_CLK_MAIN_PLL_C5, 0194 /*!< \b Main PLL C5 Output */ 0195 0196 ALT_CLK_MPU, 0197 /*!< \b mpu_clk 0198 * Main PLL C0 Output. Clock for MPU 0199 * subsystem, including CPU0 and CPU1. 0200 * * Alias for \e ALT_CLK_MAIN_PLL_C0 0201 */ 0202 0203 ALT_CLK_MPU_L2_RAM, 0204 /*!< \b mpu_l2_ram_clk 0205 * Clock for MPU level 2 (L2) RAM 0206 */ 0207 0208 ALT_CLK_MPU_PERIPH, 0209 /*!< \b mpu_periph_clk 0210 * Clock for MPU snoop control unit 0211 * (SCU) peripherals, such as the 0212 * general interrupt controller (GIC) 0213 */ 0214 0215 ALT_CLK_L3_MAIN, 0216 /*!< \b main_clk 0217 * Main PLL C1 Output 0218 * * Alias for \e ALT_CLK_MAIN_PLL_C1 0219 */ 0220 0221 ALT_CLK_L3_MP, 0222 /*!< \b l3_mp_clk 0223 * Clock for L3 Master Peripheral Switch 0224 */ 0225 0226 ALT_CLK_L3_SP, 0227 /*!< \b l3_sp_clk 0228 * Clock for L3 Slave Peripheral Switch 0229 */ 0230 0231 ALT_CLK_L4_MAIN, 0232 /*!< \b l4_main_clk 0233 * Clock for L4 main bus 0234 * * Clock for DMA 0235 * * Clock for SPI masters 0236 */ 0237 0238 ALT_CLK_L4_MP, 0239 /*!< \b l4_mp_clk 0240 * Clock for L4 master peripherals (MP) bus 0241 */ 0242 0243 ALT_CLK_L4_SP, 0244 /*!< \b l4_sp_clk 0245 * Clock for L4 slave peripherals (SP) bus 0246 */ 0247 0248 ALT_CLK_DBG_BASE, 0249 /*!< \b dbg_base_clk 0250 * Main PLL C2 Output 0251 * * Alias for \e ALT_CLK_MAIN_PLL_C2 0252 */ 0253 0254 ALT_CLK_DBG_AT, 0255 /*!< \b dbg_at_clk 0256 * Clock for CoreSight debug Advanced 0257 * Microcontroller Bus Architecture 0258 * (AMBA) Trace Bus (ATB) 0259 */ 0260 0261 ALT_CLK_DBG_TRACE, 0262 /*!< \b dbg_trace_clk 0263 * Clock for CoreSight debug Trace 0264 * Port Interface Unit (TPIU) 0265 */ 0266 0267 ALT_CLK_DBG_TIMER, 0268 /*!< \b dbg_timer_clk 0269 * Clock for the trace timestamp 0270 * generator 0271 */ 0272 0273 ALT_CLK_DBG, 0274 /*!< \b dbg_clk 0275 * Clock for Debug Access Port (DAP) 0276 * and debug Advanced Peripheral Bus 0277 * (APB) 0278 */ 0279 0280 ALT_CLK_MAIN_QSPI, 0281 /*!< \b main_qspi_clk 0282 * Main PLL C3 Output. Quad SPI flash 0283 * internal logic clock. 0284 * * Alias for \e ALT_CLK_MAIN_PLL_C3 0285 */ 0286 0287 ALT_CLK_MAIN_NAND_SDMMC, 0288 /*!< \b main_nand_sdmmc_clk 0289 * Main PLL C4 Output. Input clock to 0290 * flash controller clocks block. 0291 * * Alias for \e ALT_CLK_MAIN_PLL_C4 0292 */ 0293 0294 ALT_CLK_CFG, 0295 /*!< \b cfg_clk 0296 * FPGA manager configuration clock. 0297 */ 0298 0299 ALT_CLK_H2F_USER0, 0300 /*!< \b h2f_user0_clock 0301 * Clock to FPGA fabric 0302 */ 0303 0304 0305 /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */ 0306 ALT_CLK_PERIPHERAL_PLL_C0, 0307 /*!< \b Peripheral PLL C0 Output */ 0308 0309 ALT_CLK_PERIPHERAL_PLL_C1, 0310 /*!< \b Peripheral PLL C1 Output */ 0311 0312 ALT_CLK_PERIPHERAL_PLL_C2, 0313 /*!< \b Peripheral PLL C2 Output */ 0314 0315 ALT_CLK_PERIPHERAL_PLL_C3, 0316 /*!< \b Peripheral PLL C3 Output */ 0317 0318 ALT_CLK_PERIPHERAL_PLL_C4, 0319 /*!< \b Peripheral PLL C4 Output */ 0320 0321 ALT_CLK_PERIPHERAL_PLL_C5, 0322 /*!< \b Peripheral PLL C5 Output */ 0323 0324 ALT_CLK_USB_MP, 0325 /*!< \b usb_mp_clk 0326 * Clock for USB 0327 */ 0328 0329 ALT_CLK_SPI_M, 0330 /*!< \b spi_m_clk 0331 * Clock for L4 SPI master bus 0332 */ 0333 0334 ALT_CLK_QSPI, 0335 /*!< \b qspi_clk 0336 * Clock for Quad SPI 0337 */ 0338 0339 ALT_CLK_NAND_X, 0340 /*!< \b nand_x_clk 0341 * NAND flash controller master and 0342 * slave clock 0343 */ 0344 0345 ALT_CLK_NAND, 0346 /*!< \b nand_clk 0347 * Main clock for NAND flash 0348 * controller 0349 */ 0350 0351 ALT_CLK_SDMMC, 0352 /*!< \b sdmmc_clk 0353 * Clock for SD/MMC logic input clock 0354 */ 0355 0356 ALT_CLK_EMAC0, 0357 /*!< \b emac0_clk 0358 * EMAC 0 clock - Peripheral PLL C0 0359 * Output 0360 * * Alias for \e ALT_CLK_PERIPHERAL_PLL_C0 0361 */ 0362 0363 ALT_CLK_EMAC1, 0364 /*!< \b emac1_clk 0365 * EMAC 1 clock - Peripheral PLL C1 0366 * Output 0367 * * Alias for \e ALT_CLK_PERIPHERAL_PLL_C1 0368 */ 0369 0370 ALT_CLK_CAN0, 0371 /*!< \b can0_clk 0372 * Controller area network (CAN) 0373 * controller 0 clock 0374 */ 0375 0376 ALT_CLK_CAN1, 0377 /*!< \b can1_clk 0378 * Controller area network (CAN) 0379 * controller 1 clock 0380 */ 0381 0382 ALT_CLK_GPIO_DB, 0383 /*!< \b gpio_db_clk 0384 * Debounce clock for GPIO0, GPIO1, 0385 * and GPIO2 0386 */ 0387 0388 ALT_CLK_H2F_USER1, 0389 /*!< \b h2f_user1_clock 0390 * Clock to FPGA fabric - Peripheral 0391 * PLL C5 Output 0392 * * Alias for \e ALT_CLK_PERIPHERAL_PLL_C5 0393 */ 0394 0395 0396 /* SDRAM Clock Group - The following clocks are derived from the SDRAM PLL */ 0397 ALT_CLK_SDRAM_PLL_C0, 0398 /*!< \b SDRAM PLL C0 Output */ 0399 0400 ALT_CLK_SDRAM_PLL_C1, 0401 /*!< \b SDRAM PLL C1 Output */ 0402 0403 ALT_CLK_SDRAM_PLL_C2, 0404 /*!< \b SDRAM PLL C2 Output */ 0405 0406 ALT_CLK_SDRAM_PLL_C3, 0407 /*!< \b SDRAM PLL C3 Output */ 0408 0409 ALT_CLK_SDRAM_PLL_C4, 0410 /*!< \b SDRAM PLL C4 Output */ 0411 0412 ALT_CLK_SDRAM_PLL_C5, 0413 /*!< \b SDRAM PLL C5 Output */ 0414 0415 ALT_CLK_DDR_DQS, 0416 /*!< \b ddr_dqs_clk 0417 * Clock for MPFE, single-port 0418 * controller, CSR access, and PHY - 0419 * SDRAM PLL C0 Output 0420 * * Alias for \e ALT_CLK_SDRAM_PLL_C0 0421 */ 0422 0423 ALT_CLK_DDR_2X_DQS, 0424 /*!< \b ddr_2x_dqs_clk 0425 * Clock for PHY - SDRAM PLL C1 Output 0426 * * Alias for \e ALT_CLK_SDRAM_PLL_C1 0427 */ 0428 0429 ALT_CLK_DDR_DQ, 0430 /*!< \b ddr_dq_clk 0431 * Clock for PHY - SDRAM PLL C2 Output 0432 * * Alias for \e ALT_CLK_SDRAM_PLL_C2 0433 */ 0434 0435 ALT_CLK_H2F_USER2, 0436 /*!< \b h2f_user2_clock 0437 * Clock to FPGA fabric - SDRAM PLL C5 0438 * Output 0439 * * Alias for \e ALT_CLK_SDRAM_PLL_C5 0440 */ 0441 0442 /* Clock Output Pins */ 0443 ALT_CLK_OUT_PIN_EMAC0_TX, 0444 /*!< \b EMAC0:TX_CLK 0445 * Tx Reference Clock for EMAC0 0446 * * Output Pin 0447 */ 0448 0449 ALT_CLK_OUT_PIN_EMAC1_TX, 0450 /*!< \b EMAC1:TX_CLK 0451 * Tx Reference Clock for EMAC1 0452 * * Output Pin 0453 */ 0454 0455 ALT_CLK_OUT_PIN_SDMMC, 0456 /*!< \b SDMMC:CLK 0457 * SD/MMC Card Clock 0458 * * Output Pin 0459 */ 0460 0461 ALT_CLK_OUT_PIN_I2C0_SCL, 0462 /*!< \b I2C0:SCL 0463 * I2C Clock for I2C0 0464 * * Output Pin 0465 */ 0466 0467 ALT_CLK_OUT_PIN_I2C1_SCL, 0468 /*!< \b I2C1:SCL 0469 * I2C Clock for I2C1 0470 * * Output Pin 0471 */ 0472 0473 ALT_CLK_OUT_PIN_I2C2_SCL, 0474 /*!< \b I2C2:SCL 0475 * I2C Clock for I2C2/2 wire 0476 * * Output Pin 0477 */ 0478 0479 ALT_CLK_OUT_PIN_I2C3_SCL, 0480 /*!< \b I2C3:SCL 0481 * I2C Clock for I2C1/2 wire 0482 * * Output Pin 0483 */ 0484 0485 ALT_CLK_OUT_PIN_SPIM0, 0486 /*!< \b SPIM0:CLK 0487 * SPI Clock 0488 * * Output Pin 0489 */ 0490 0491 ALT_CLK_OUT_PIN_SPIM1, 0492 /*!< \b SPIM1:CLK 0493 * SPI Clock 0494 * * Output Pin 0495 */ 0496 0497 ALT_CLK_OUT_PIN_QSPI, 0498 /*!< \b QSPI:CLK 0499 * QSPI Flash Clock 0500 * * Output Pin 0501 */ 0502 0503 ALT_CLK_UNKNOWN 0504 } ALT_CLK_t; 0505 0506 /******************************************************************************/ 0507 /*! \addtogroup CLK_MGR_STATUS Clock Manager Status 0508 * 0509 * This functional group provides status information on various aspects and 0510 * properties of the Clock Manager state. 0511 * 0512 * @{ 0513 */ 0514 /******************************************************************************/ 0515 /*! 0516 * This type definition defines the lock condition status codes for each of the 0517 * PLLs. If the PLL lock status condition is enabled (See: alt_clk_irq_enable()) 0518 * then it contributes to the overall \b clkmgr_IRQ signal assertion state. 0519 */ 0520 typedef enum ALT_CLK_PLL_LOCK_STATUS_e 0521 { 0522 ALT_MAIN_PLL_LOCK_ACHV = 0x00000001, /*!< This condition is set if the Main 0523 * PLL has achieved lock at least once 0524 * since this condition was last 0525 * cleared. 0526 */ 0527 ALT_PERIPH_PLL_LOCK_ACHV = 0x00000002, /*!< This condition is set if the Peripheral 0528 * PLL has achieved lock at least once 0529 * since this condition was last 0530 * cleared. 0531 */ 0532 ALT_SDR_PLL_LOCK_ACHV = 0x00000004, /*!< This condition is set if the SDRAM 0533 * PLL has achieved lock at least once 0534 * since this condition was last 0535 * cleared. 0536 */ 0537 ALT_MAIN_PLL_LOCK_LOST = 0x00000008, /*!< This condition is set if the Main 0538 * PLL has lost lock at least once 0539 * since this condition was last 0540 * cleared. 0541 */ 0542 ALT_PERIPH_PLL_LOCK_LOST = 0x00000010, /*!< This condition is set if the Peripheral 0543 * PLL has lost lock at least once 0544 * since this condition was last 0545 * cleared. 0546 */ 0547 ALT_SDR_PLL_LOCK_LOST = 0x00000020 /*!< This condition is set if the SDRAM 0548 * PLL has lost lock at least once 0549 * since this condition was last 0550 * cleared. 0551 */ 0552 } ALT_CLK_PLL_LOCK_STATUS_t; 0553 0554 /******************************************************************************/ 0555 /*! 0556 * Clear the selected PLL lock status conditions. 0557 * 0558 * This function clears assertions of one or more of the PLL lock status 0559 * conditions. 0560 * 0561 * NOTE: This function is used to clear \b clkmgr_IRQ interrupt signal source 0562 * assertion conditions. 0563 * 0564 * \param lock_stat_mask 0565 * Specifies the PLL lock status conditions to clear. \e lock_stat_mask 0566 * is a mask of logically OR'ed \ref ALT_CLK_PLL_LOCK_STATUS_t 0567 * values designating the PLL lock conditions to clear. 0568 * 0569 * \retval ALT_E_SUCCESS Successful status. 0570 * \retval ALT_E_BAD_ARG The \e lock_stat_mask argument contains an 0571 * unknown condition value. 0572 */ 0573 ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask); 0574 0575 /******************************************************************************/ 0576 /*! 0577 * Returns the PLL lock status condition values. 0578 * 0579 * This function returns the value of the PLL lock status conditions. 0580 * 0581 * \returns The current values of the PLL lock status conditions as defined by 0582 * the \ref ALT_CLK_PLL_LOCK_STATUS_t mask bits. If the corresponding bit is set 0583 * then the condition is asserted. 0584 */ 0585 uint32_t alt_clk_lock_status_get(void); 0586 0587 /******************************************************************************/ 0588 /*! 0589 * Returns ALT_E_TRUE if the designated PLL is currently locked and ALT_E_FALSE 0590 * otherwise. 0591 * 0592 * \param pll 0593 * The PLL to return the lock status of. 0594 * 0595 * \retval ALT_E_TRUE The specified PLL is currently locked. 0596 * \retval ALT_E_FALSE The specified PLL is currently not locked. 0597 * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock 0598 * value. 0599 * \internal 0600 * NOTE: This function uses the 0601 * * \b hps::clkmgr::inter::mainplllocked 0602 * * \b hps::clkmgr::inter::perplllocked, 0603 * * \b hps::clkmgr::inter::sdrplllocked 0604 * 0605 * bits to determine if the PLL is locked or not. 0606 * \endinternal 0607 */ 0608 ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll); 0609 0610 /*! @} */ 0611 0612 /******************************************************************************/ 0613 /*! \addtogroup CLK_MGR_SAFE_MODE Safe Mode Options 0614 * 0615 * When safe mode is enabled, clocks in the HPS are directly generated from the 0616 * \b osc1_clk clock. Safe mode is enabled by the assertion of a safe mode 0617 * request from the reset manager or by a cold reset. Assertion of the safe mode 0618 * request from the reset manager sets the safe mode bit in the clock manager 0619 * control register. No other control register bits are affected by the safe 0620 * mode request from the reset manager. 0621 * 0622 * While in safe mode, clock manager register settings which control clock 0623 * behavior are not changed. However, the output of the registers which control 0624 * the clock manager state are forced to the safe mode values such that the 0625 * following conditions occur: 0626 * * All PLLs are bypassed to the \b osc1_clk clock, including their counters. 0627 * * Clock dividers select their default reset values. 0628 * * The flash controllers source clock selections are set to the peripheral 0629 * PLL. 0630 * * All clocks are enabled. 0631 * * Safe mode is optionally applied to debug clocks. 0632 * 0633 * A write by software is the only way to clear the safe mode bit. All registers 0634 * and clocks need to be configured correctly and all software-managed clocks 0635 * need to be gated off before clearing safe mode. Software can then gate clocks 0636 * on as required. 0637 * 0638 * On cold reset, all clocks are put in safe mode. 0639 * 0640 * On warm reset, safe mode is optionally and independently applied to debug 0641 * clocks and normal (i.e.non-debug) clocks based on clock manager register 0642 * settings. The default response for warm reset is to put all clocks in safe 0643 * mode. 0644 * 0645 * The APIs in this group provide control of the Clock Manager safe mode warm 0646 * reset response behavior. 0647 * @{ 0648 */ 0649 0650 /******************************************************************************/ 0651 /*! 0652 * This type definition enumerates the safe mode clock domains under control of 0653 * the Clock Manager. 0654 */ 0655 typedef enum ALT_CLK_SAFE_DOMAIN_e 0656 { 0657 /*! 0658 * This enumeration literal specifies the normal safe mode domain. The 0659 * normal domain consists of all clocks except debug clocks. 0660 */ 0661 ALT_CLK_DOMAIN_NORMAL, 0662 /*! 0663 * This enumeration literal specifies the debug safe mode domain. The debug 0664 * domain consists of all debug clocks. 0665 */ 0666 ALT_CLK_DOMAIN_DEBUG 0667 } ALT_CLK_SAFE_DOMAIN_t; 0668 0669 /******************************************************************************/ 0670 /*! 0671 * Clear the safe mode status of the Clock Manager following a reset. 0672 * 0673 * NOTE: Safe mode should only be cleared once clocks have been correctly 0674 * configured. 0675 * 0676 * \retval ALT_E_SUCCESS The operation was succesful. 0677 * \retval ALT_E_ERROR The operation failed. 0678 */ 0679 ALT_STATUS_CODE alt_clk_safe_mode_clear(void); 0680 0681 /******************************************************************************/ 0682 /*! 0683 * Return whether the specified safe mode clock domain is in safe mode or not. 0684 * 0685 * \param clk_domain 0686 * The safe mode clock domain to check whether in safe mode or not. 0687 * 0688 * \retval TRUE The safe mode clock domain is in safe mode. 0689 * \retval FALSE The safe mode clock domain is not in safe mode. 0690 */ 0691 bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain); 0692 0693 /*! @} */ 0694 0695 /******************************************************************************/ 0696 /*! \addtogroup CLK_MGR_BYPASS PLL Bypass Control 0697 * 0698 * When a PLL is in bypass, the PLL clock logic is kept in reset. In this 0699 * manner, the PLL clock can be free running while it stabilizes and achieves 0700 * lock. The bypass logic isolates PLL configuration registers from the clock 0701 * while changes are made to the PLL settings. 0702 * 0703 * The bypass controls are used by software to change the source clock input 0704 * reference (for Peripheral and SDRAM PLLs) and is recommended when changing 0705 * settings that may affect the ability of the VCO to maintain lock. When a PLL 0706 * is taken in or out of bypass the PLL output clocks will pause momentarily 0707 * while the clocks are in transition, There will be no glitches or clocks 0708 * shorter than the either the old or the new clock period. 0709 * 0710 * In summary, the PLL bypass controls permit: 0711 * * Each PLL to be individually bypassed. 0712 * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs 0713 * reference clock input source reference clock selection. 0714 * * Isolation of a the PLL VCO frequency registers (multiplier and divider), 0715 phase shift registers (negative phase) , and post scale counters. 0716 * * Glitch free clock transitions. 0717 * @{ 0718 */ 0719 /******************************************************************************/ 0720 /*! 0721 * Disable bypass mode for the specified PLL. This operation takes the PLL out 0722 * of bypass mode. 0723 * 0724 * \param pll 0725 * The PLL to take out of bypass mode. 0726 * 0727 * \retval ALT_E_SUCCESS The operation was succesful. 0728 * \retval ALT_E_ERROR The operation failed. 0729 * \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL clock 0730 * value. 0731 */ 0732 ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll); 0733 0734 /******************************************************************************/ 0735 /*! 0736 * Enable bypass mode for the specified PLL. 0737 * 0738 * \param pll 0739 * The PLL to put into bypass mode. 0740 * 0741 * \param use_input_mux 0742 * If TRUE then use the PLLs reference clock input source selection 0743 * to directly drive the bypass clock. If FALSE then use bypass 0744 * clock directly driven by the \b osc1_clk. 0745 * 0746 * \retval ALT_E_SUCCESS The operation was succesful. 0747 * \retval ALT_E_ERROR The operation failed. 0748 * \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL 0749 * clock value. 0750 * \retval ALT_E_INV_OPTION TRUE is an invalid option for 0751 * \e use_input_mux with the \e pll selection. 0752 */ 0753 ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, 0754 bool use_input_mux); 0755 0756 /******************************************************************************/ 0757 /*! 0758 * Return whether the specified PLL is in bypass or not. 0759 * 0760 * \internal 0761 * This function must also test the \b clkmgr.ctrl.safemode bit in 0762 * addition to the PLLs bypass bit to tell whether the bypass mode is 0763 * effect or not. 0764 * \endinternal 0765 * 0766 * \param pll 0767 * The PLL to check whether in bypass mode or not. 0768 * 0769 * \retval ALT_E_TRUE The PLL is in bypass mode. 0770 * \retval ALT_E_FALSE The PLL is not in bypass mode. 0771 * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock 0772 * value. 0773 */ 0774 ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll); 0775 0776 /*! @} */ 0777 0778 /******************************************************************************/ 0779 /*! \addtogroup CLK_MGR_GATE Clock Gating Control 0780 * 0781 * This functional group provides gating control of selected clock signals. 0782 * 0783 * When a clock is enabled, then its clock signal propogates to its respective 0784 * clocked IP block(s). When a clock is disabled, then its clock signal is 0785 * prevented from propogating to its respective clocked IP block(s). 0786 * 0787 * The following clocks may be gated: 0788 * 0789 * * Main PLL Group 0790 * - l4_main_clk 0791 * - l3_mp_clk 0792 * - l4_mp_clk 0793 * - l4_sp_clk 0794 * - dbg_at_clk 0795 * - dbg_clk 0796 * - dbg_trace_clk 0797 * - dbg_timer_clk 0798 * - cfg_clk 0799 * - s2f_user0_clk 0800 * 0801 * * SDRAM PLL Group 0802 * - ddr_dqs_clk 0803 * - ddr_2x_clk 0804 * - ddr_dq_clk 0805 * - s2f_user2_clk 0806 * 0807 * * Peripheral PLL Group 0808 * - emac0_clk 0809 * - emac1_clk 0810 * - usb_mp_clk 0811 * - spi_m_clk 0812 * - can0_clk 0813 * - can1_clk 0814 * - gpio_db_clk 0815 * - s2f_user1_clk 0816 * - sdmmc_clk 0817 * - nand_clk 0818 * - nand_x_clk 0819 * - qspi_clk 0820 * 0821 * @{ 0822 */ 0823 /******************************************************************************/ 0824 /*! 0825 * Disable the specified clock. Once the clock is disabled, its clock signal does 0826 * not propogate to its clocked elements. 0827 * 0828 * \param clk 0829 * The clock to disable. 0830 * 0831 * \retval ALT_E_SUCCESS The operation was succesful. 0832 * \retval ALT_E_ERROR The operation failed. 0833 * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock 0834 * value. 0835 */ 0836 ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk); 0837 0838 /******************************************************************************/ 0839 /*! 0840 * Enable the specified clock. Once the clock is enabled, its clock signal 0841 * propogates to its elements. 0842 * 0843 * \param clk 0844 * The clock to enable. 0845 * 0846 * \retval ALT_E_SUCCESS The operation was succesful. 0847 * \retval ALT_E_ERROR The operation failed. 0848 * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock 0849 * value. 0850 */ 0851 ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk); 0852 0853 /******************************************************************************/ 0854 /*! 0855 * Return whether the specified clock is enabled or not. 0856 * 0857 * \param clk 0858 * The clock to check whether enabled or not. 0859 * 0860 * \retval ALT_E_TRUE The clock is enabled. 0861 * \retval ALT_E_FALSE The clock is not enabled. 0862 * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock 0863 * value. 0864 */ 0865 ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk); 0866 0867 /*! @} */ 0868 0869 /******************************************************************************/ 0870 /*! \addtogroup CLK_MGR_CLK_SEL Clock Source Selection 0871 * 0872 * This API group provide access and control to the input reference clock source 0873 * selection for a clock or PLL. 0874 * 0875 * \internal 0876 * These are the clocks that have software configurable input reference clock 0877 * source selection available. Each clock below is listed with its valid 0878 * input reference clock source selections. 0879 * 0880 * + Valid reference clock input selections for \b sdram_pll_ref_clkin 0881 * - osc_clk_1 0882 * - osc_clk_2 0883 * - f2h_sdram_ref_clk 0884 * 0885 * + Valid reference clock input selections for \b periph_pll_ref_clkin 0886 * - osc_clk_1 0887 * - osc_clk_2, 0888 * - f2h_periph_ref_clk 0889 * 0890 * + Valid reference clock input selections for \b l4_mp_clk 0891 * - periph_base_clk 0892 * - main_clk 0893 * 0894 * + Valid reference clock input selections for \b l4_sp_clk 0895 * - periph_base_clk 0896 * - main_clk 0897 * 0898 * + Valid reference clock input selections for \b sdmmc_clk 0899 * - f2h_periph_ref_clk 0900 * - main_nand_sdmmc_clk 0901 * - periph_nand_sdmmc_clk 0902 * 0903 * + Valid reference clock input selections for \b nand_clk 0904 * - f2h_periph_ref_clk 0905 * - main_nand_sdmmc_clk 0906 * - periph_nand_sdmmc_clk 0907 * 0908 * + Valid reference clock input selections for \b qspi_clk 0909 * - f2h_periph_ref_clk 0910 * - main_qspi_clk 0911 * - periph_qspi_clk 0912 * 0913 * \endinternal 0914 * @{ 0915 */ 0916 /******************************************************************************/ 0917 /*! 0918 * Get the input reference clock source selection value for the specified clock 0919 * or PLL. 0920 * 0921 * NOTE: This function returns a clock value even though \e clk may specify a 0922 * clock that does not have a selectable input reference clock source. In 0923 * this case, the clock value returned is the static clock source for the 0924 * specified clock. For example calling alt_clk_source_get() with \e clk 0925 * set to \ref ALT_CLK_MAIN_PLL will return \ref ALT_CLK_OSC1. 0926 * 0927 * \param clk 0928 * The clock or PLL to retrieve the input reference clock source 0929 * selection value for. 0930 * 0931 * \returns The clock's currently selected input reference clock source. 0932 */ 0933 ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk); 0934 0935 /******************************************************************************/ 0936 /*! 0937 * Set the specified clock's input reference clock source selection. 0938 * 0939 * \param clk 0940 * The clock or PLL to set the input reference clock source 0941 * selection for. 0942 * 0943 * \param ref_clk 0944 * The input reference clock source selection value. 0945 * 0946 * \retval ALT_E_SUCCESS The operation was succesful. 0947 * \retval ALT_E_ERROR The operation failed. 0948 * \retval ALT_E_BAD_ARG The \e clk argument designates a clock that 0949 * does not have a selectable input reference 0950 * clock source. 0951 * \retval ALT_E_INV_OPTION The \e ref_clk argument designates a clock that 0952 * is an invalid reference clock source for the 0953 * specified clock. 0954 */ 0955 ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, 0956 ALT_CLK_t ref_clk); 0957 0958 /*! @} */ 0959 0960 /******************************************************************************/ 0961 /*! \addtogroup CLK_MGR_FREQ Clock Frequency Control 0962 * 0963 * This API group provides access and control of the output frequency of a clock 0964 * or PLL. 0965 * 0966 * @{ 0967 */ 0968 0969 /******************************************************************************/ 0970 /*! 0971 * Set the external clock frequency value. 0972 * 0973 * The function is used to specify the frequency of the external clock source as 0974 * a measure of Hz. The supplied frequency should be within the Fmin and Fmax 0975 * values allowed for the external clock source. 0976 * 0977 * \param clk 0978 * The external clock source. Valid external clocks are 0979 * * \e ALT_CLK_OSC1 0980 * * \e ALT_CLK_OSC2 0981 * * \e ALT_CLK_F2H_PERIPH_REF 0982 * * \e ALT_CLK_F2H_SDRAM_REF 0983 * 0984 * \param freq 0985 * The frequency of the external clock in Hz. 0986 * 0987 * \retval ALT_E_SUCCESS The operation was succesful. 0988 * \retval ALT_E_ERROR The operation failed. 0989 * \retval ALT_E_BAD_ARG A bad argument value was passed. Either the \e clk 0990 * argument is bad or not a valid external clock 0991 * source 0992 * \retval ALT_E_ARG_RANGE The frequency value violates the range constraints 0993 * for the specified clock. 0994 0995 */ 0996 ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk, 0997 alt_freq_t freq); 0998 0999 /******************************************************************************/ 1000 /*! 1001 * Get the external clock frequency value. 1002 * 1003 * This function returns the frequency of the external clock source as 1004 * a measure of Hz. 1005 * 1006 * \param clk 1007 * The external clock source. Valid external clocks are 1008 * * \e ALT_CLK_OSC1 1009 * * \e ALT_CLK_OSC2 1010 * * \e ALT_CLK_F2H_PERIPH_REF 1011 * * \e ALT_CLK_F2H_SDRAM_REF 1012 * 1013 * \retval freq 1014 * The frequency of the external clock in Hz. 1015 * 1016 */ 1017 alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk); 1018 1019 /******************************************************************************/ 1020 /*! 1021 * This type definition defines a structure to contain the generalized 1022 * configuration settings for a PLL. 1023 */ 1024 typedef struct ALT_CLK_PLL_CFG_s 1025 { 1026 ALT_CLK_t ref_clk; /*!< PLL Reference Clock Source */ 1027 uint32_t mult; /*!< VCO Frequency Configuration - 1028 * Multiplier (M) value, range 1 to 4096 1029 */ 1030 uint32_t div; /*!< VCO Frequency Configuration - 1031 * Divider (N) value, range 1 to 64 1032 */ 1033 uint32_t cntrs[6]; /*!< Post-Scale Counters (C0 - C5) - 1034 * range 1 to 512 1035 */ 1036 uint32_t pshift[6]; /*!< Phase Shift - 1/8 (45 degrees) of 1037 * negative phase shift per increment, 1038 * range 0 to 4096 1039 */ 1040 } ALT_CLK_PLL_CFG_t; 1041 1042 /******************************************************************************/ 1043 /*! 1044 * Get the current PLL configuration. 1045 * 1046 * \param pll 1047 * The PLL to get the configuration from. 1048 * 1049 * \param pll_cfg 1050 * [out] Pointer to an output parameter variable for the returned 1051 * PLL configuration. 1052 * 1053 * \retval ALT_E_SUCCESS The operation was succesful. 1054 * \retval ALT_E_ERROR The operation failed. 1055 */ 1056 ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll, 1057 ALT_CLK_PLL_CFG_t* pll_cfg); 1058 1059 /******************************************************************************/ 1060 /*! 1061 * Set the PLL configuration using the configuration parameters specified in 1062 * \e pll_cfg. 1063 * 1064 * \param pll 1065 * The PLL to set the configuration for. 1066 * 1067 * \param pll_cfg 1068 * Pointer to a ALT_CLK_PLL_CFG_t structure specifying the desired 1069 * PLL configuration. 1070 * 1071 * \retval ALT_E_SUCCESS The operation was succesful. 1072 * \retval ALT_E_ERROR The operation failed. 1073 */ 1074 ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll, 1075 const ALT_CLK_PLL_CFG_t* pll_cfg); 1076 1077 /******************************************************************************/ 1078 /*! 1079 * Get the current PLL VCO frequency configuration. 1080 * 1081 * \param pll 1082 * The PLL to get the VCO frequency configuration for. 1083 * 1084 * \param mult 1085 * [out] Pointer to an output variable for the returned 1086 * configured PLL VCO multiplier (M) value. 1087 * 1088 * \param div 1089 * [out] Pointer to an output variable for the returned 1090 * configured PLL VCO divider (N) value. 1091 * 1092 * \retval ALT_E_SUCCESS The operation was succesful. 1093 * \retval ALT_E_ERROR The operation failed. 1094 */ 1095 ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll, 1096 uint32_t* mult, 1097 uint32_t* div); 1098 1099 /******************************************************************************/ 1100 /*! 1101 * Set the PLL VCO frequency configuration using the supplied multiplier and 1102 * divider arguments. 1103 * 1104 * \param pll 1105 * The PLL to set the VCO frequency configuration for. 1106 * 1107 * \param mult 1108 * The PLL VCO multiplier (M). Expected argument range 1 to 4096. 1109 * 1110 * \param div 1111 * The PLL VCO divider (N). Expected argument range 1 to 64. 1112 * 1113 * \retval ALT_E_SUCCESS The operation was succesful. 1114 * \retval ALT_E_ERROR The operation failed. 1115 */ 1116 ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll, 1117 uint32_t mult, 1118 uint32_t div); 1119 1120 /******************************************************************************/ 1121 /*! 1122 * Get the VCO frequency of the specified PLL. 1123 * 1124 * \param pll 1125 * The PLL to retrieve the VCO frequency from. 1126 * 1127 * \param freq 1128 * [out] Pointer to the an output parameter variable to return the 1129 * PLL VCO frequency value. The frequency value is returned as a 1130 * measures of Hz. 1131 * 1132 * \retval ALT_E_SUCCESS The operation was succesful. 1133 * \retval ALT_E_ERROR The operation failed. 1134 * \retval ALT_E_BAD_ARG A bad argument value was passed. Either 1135 * the \e pll argument is invalid or a bad 1136 * \e freq pointer value was passed. 1137 */ 1138 ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll, 1139 alt_freq_t* freq); 1140 1141 /******************************************************************************/ 1142 /*! 1143 * Get the PLL frequency guard band value. 1144 * 1145 * \param pll 1146 * The PLL from which to return the current guard band value. 1147 * 1148 * \returns The current guard band range in effect for the PLL. 1149 */ 1150 uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll); 1151 1152 /******************************************************************************/ 1153 /*! 1154 * Set the PLL frequency guard band value. 1155 * 1156 * Once a PLL has achieved lock, any changes to the PLL VCO frequency that are 1157 * within a specific guard band range (default value 20%) of the reference 1158 * period should not cause the PLL to lose lock. 1159 * 1160 * Programmatic changes to the PLL frequency within this guard band range are 1161 * permitted to be made without the risk of breaking lock during the transition 1162 * to the new frequency. 1163 * 1164 * The clk_mgr_pll_guard_band_set() function changes the guard band from its 1165 * current value to permit a more lenient or stringent policy to be in effect in 1166 * the implementation of the functions configuring PLL VCO frequency. The 1167 * rationale for changing the default guard band value might be to accommodate 1168 * unexpected environmental conditions (noise, temperature, and other 1169 * instability factors) that may affect the PLLs ability to maintain lock during 1170 * a frequency change. 1171 * 1172 * \param pll 1173 * The PLL to set the guard band value for. 1174 * 1175 * \param guard_band 1176 * The guard band value. Value should be 0 <= \e guard_band <= 100. 1177 * 1178 * \retval ALT_E_SUCCESS The operation was succesful. 1179 * \retval ALT_E_ERROR The operation failed. 1180 * \retval ALT_E_ARG_RANGE The guard band value violates its range constraint. 1181 */ 1182 ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll, 1183 uint32_t guard_band); 1184 1185 /******************************************************************************/ 1186 /*! 1187 * Get the configured divider value for the specified clock. 1188 * 1189 * This function is used to get the configured values of both internal and 1190 * external clock dividers. The internal divider (PLL counters C0-C5) values 1191 * are retrieved by specifying the clock name that is the divider output 1192 * (e.g. ALT_CLK_MPU is used to get the Main PLL C0 counter value). \n 1193 * It returns the actual divider value, not the encoded bitfield stored 1194 * in the register, due to the variety of different encodings. 1195 * 1196 * \param clk 1197 * The clock divider to get the value from. 1198 * 1199 * \param div 1200 * [out] Pointer to an output variable for the returned clock 1201 * divider value. 1202 * 1203 * \retval ALT_E_SUCCESS The operation was succesful. 1204 * \retval ALT_E_ERROR The operation failed. 1205 * \retval ALT_E_BAD_ARG An invalid clock argument was specified or a 1206 * clock that does not have a divider. 1207 */ 1208 ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk, 1209 uint32_t* div); 1210 1211 /******************************************************************************/ 1212 /*! 1213 * Set the divider value for the specified clock. 1214 * 1215 * This function is used to set the values of both internal and external clock 1216 * dividers. The internal divider (PLL counters C0-C5) values are set by 1217 * specifying the clock name that is the divider output (e.g. ALT_CLK_MPU is 1218 * used to set the Main PLL C0 counter value). 1219 * 1220 * \param clk 1221 * The clock divider to set the value for. 1222 * 1223 * \param div 1224 * The clock divider value. NOTE: The valid range of clock divider 1225 * values depends on the clock being configured. This is the 1226 * real divisor ratio, not how the divisor is coded into the 1227 * register, and is always one or greater. 1228 * 1229 * \retval ALT_E_SUCCESS The operation was succesful. 1230 * \retval ALT_E_ERROR The operation failed. 1231 * \retval ALT_E_BAD_ARG An invalid clock argument was specified or a 1232 * clock that does not have a divider. 1233 * \retval ALT_E_ARG_RANGE The divider value violates the range constraints 1234 * for the clock divider. 1235 */ 1236 ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk, 1237 uint32_t div); 1238 1239 /******************************************************************************/ 1240 /*! 1241 * Get the output frequency of the specified clock. 1242 * 1243 * \param clk 1244 * The clock to retrieve the output frequency from. 1245 * 1246 * \param freq 1247 * [out] Pointer to the an output parameter variable to return the 1248 * clock output frequency value. The frequency value is returned as 1249 * a measures of Hz. 1250 * 1251 * \retval ALT_E_SUCCESS The operation was succesful. 1252 * \retval ALT_E_ERROR The operation failed. 1253 * \retval ALT_E_BAD_ARG A bad argument value was passed. Either 1254 * the \e clk argument is invalid or a bad 1255 * \e freq pointer value was passed. 1256 */ 1257 ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk, 1258 alt_freq_t* freq); 1259 1260 /*! @} */ 1261 1262 /******************************************************************************/ 1263 /*! \addtogroup CLK_MGR_INT Clock Manager Interrupt Management 1264 * 1265 * The functions in this group provide management of interrupts originating from 1266 * the Clock Manager. 1267 * 1268 * The following interrupt request (IRQ) signals are sourced from the Clock 1269 * Manager: 1270 * 1271 * * \b clkmgr_IRQ - Clock Manager lock status interrupt output. The PLL lock 1272 * status interrupt is the logical \e OR of six interrupt 1273 * sources defining the loss or achievement of lock status for 1274 * each PLL. The six PLL lock status conditions are: 1275 * - Main PLL Achieved Lock 1276 * - Main PLL Lost Lock 1277 * - Peripheral PLL Achieved Lock 1278 * - Peripheral PLL Lost Lock 1279 * - SDRAM PLL Achieved Lock 1280 * - SDRAM PLL Lost Lock 1281 * 1282 * They are enumeratated by the type \ref ALT_CLK_PLL_LOCK_STATUS_t. 1283 * 1284 * Each PLL lock condition may be individually disabled/enabled 1285 * as a contributor to the determination of the \b clkmgr_IRQ 1286 * assertion status. 1287 * 1288 * The alt_clk_lock_status_clear() function is used to clear 1289 * the PLL lock conditions causing the \b clkmgr_IRQ 1290 * assertion. 1291 * 1292 * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the 1293 * MPU to "wake up" after a transition of the Main PLL into 1294 * or out of bypass mode has been safely achieved. The need 1295 * for the "wake up" notification is because the PLL clocks 1296 * pause for a short number of clock cycles during bypass 1297 * state transition. ARM recommeds that the CPUs are placed 1298 * in standby if the clocks are ever paused. 1299 * 1300 * NOTE: \b mpuwakeup_IRQ appears to be an Altera private interrupt and may not 1301 * be part of the public API although clearly it has important utility in 1302 * implementing safe changes to PLL settings and transitions into and out 1303 * of bypass mode. 1304 * @{ 1305 */ 1306 1307 /******************************************************************************/ 1308 /*! 1309 * Disable the \b clkmgr_IRQ interrupt signal source lock status condition(s). 1310 * 1311 * This function disables one or more of the lock status conditions as 1312 * contributors to the \b clkmgr_IRQ interrupt signal state. 1313 * 1314 * NOTE: A set bit for a PLL lock status condition in the mask value does not 1315 * have the effect of enabling it as a contributor to the \b clkmgr_IRQ 1316 * interrupt signal state. The function alt_clk_irq_enable is used to enable PLL 1317 * lock status source condition(s). 1318 * 1319 * \param lock_stat_mask 1320 * Specifies the PLL lock status conditions to disable as interrupt 1321 * source contributors. \e lock_stat_mask is a mask of logically 1322 * OR'ed ALT_CLK_PLL_LOCK_STATUS_t values that designate the PLL lock 1323 * conditions to disable. 1324 * 1325 * \retval ALT_E_SUCCESS Successful status. 1326 * \retval ALT_E_BAD_ARG The \e lock_stat_mask argument contains an 1327 * unknown condition value. 1328 */ 1329 ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask); 1330 1331 /******************************************************************************/ 1332 /*! 1333 * Enable the \b clkmgr_IRQ interrupt signal source lock status condition(s). 1334 * 1335 * This function enables one or more of the lock status conditions as 1336 * contributors to the \b clkmgr_IRQ interrupt signal state. 1337 * 1338 * NOTE: A cleared bit for any PLL lock status condition in the mask value does 1339 * not have the effect of disabling it as a contributor to the \b clkmgr_IRQ 1340 * interrupt signal state. The function alt_clk_irq_disable is used to disable 1341 * PLL lock status source condition(s). 1342 * 1343 * \param lock_stat_mask 1344 * Specifies the PLL lock status conditions to enable as interrupt 1345 * source contributors. \e lock_stat_mask is a mask of logically 1346 * OR'ed ALT_CLK_PLL_LOCK_STATUS_t values that designate the PLL lock 1347 * conditions to enable. 1348 * 1349 * \retval ALT_E_SUCCESS Successful status. 1350 * \retval ALT_E_BAD_ARG The \e lock_stat_mask argument contains an 1351 * unknown condition value. 1352 */ 1353 ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask); 1354 1355 /*! @} */ 1356 1357 /******************************************************************************/ 1358 /*! \addtogroup CLK_MGR_GROUP_CFG Clock Group Configuration 1359 * 1360 * This API provides the ability to safely set the configuration of a clock 1361 * group with a single function call. 1362 * 1363 * A clock group is defined as set of clocks and signals generated from a common 1364 * PLL VCO. The PLL and its derived clocks are treated as a single clock 1365 * group. The clocks sourced directly or indirectly from the PLL may or may not 1366 * have these features: 1367 * * Clock Gates 1368 * * Clock Dividers 1369 * * Clock Source Selection Options 1370 * 1371 * The use case for application of the Clock Group Configuration functions is the 1372 * ability to safely configure an entire clock group from a known good clock 1373 * group configuration using the run-time function alt_clk_group_cfg_raw_set(). 1374 * 1375 * A known good clock group configuration may be generated by one of the 1376 * following methods: 1377 * 1378 * * As static design information generated by an ACDS clock configuration tool 1379 * and passed to embedded software for dynamic loading. 1380 * 1381 * * By calling alt_clk_group_cfg_raw_get() at run-time from an SoC FPGA that has 1382 * programmatically established a known good clock group configuration using 1383 * the clock manager API configuration functions. 1384 * 1385 * @{ 1386 */ 1387 1388 /******************************************************************************/ 1389 /*! 1390 * Get the raw configuration state of the designated clock group. 1391 * 1392 * This function is used to capture the configuration state of the specified 1393 * clock group in a private (raw) data structure. The raw data structure may be 1394 * saved and used later to restore the clock group configuration using 1395 * alt_clk_group_cfg_raw_get(). 1396 * 1397 * \param clk_group 1398 * The clock group configuration to capture. 1399 * 1400 * \param clk_group_raw_cfg 1401 * [out] A pointer to a private (raw) data structure to store the 1402 * captured clock group configuration. 1403 * 1404 * \retval ALT_E_SUCCESS Successful status. 1405 * \retval ALT_E_ERROR Details about error status code 1406 */ 1407 ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group, 1408 ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg); 1409 1410 /******************************************************************************/ 1411 /*! 1412 * Set the clock group configuration. 1413 * 1414 * This function is used to safely set the configuration state of a clock 1415 * group from a raw clock group configuration specification. The raw clock 1416 * group configuration specification may be a configuration previously 1417 * captured with alt_clk_group_cfg_raw_get() or a group clock configuration 1418 * generated by an external utility. 1419 * 1420 * \param clk_group_raw_cfg 1421 * A pointer to the specification to use in the configuration of 1422 * the clock group. 1423 * 1424 * \retval ALT_E_SUCCESS Successful status. 1425 * \retval ALT_E_ERROR Details about error status code 1426 * \retval ALT_E_BAD_VERSION The clock group configuration specification is 1427 * invalid for this device. 1428 */ 1429 ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg); 1430 1431 ALT_STATUS_CODE alt_clk_clkmgr_init(void); 1432 1433 /*! @} */ 1434 1435 /*! @} */ 1436 #ifdef __cplusplus 1437 } 1438 1439 #endif /* __cplusplus */ 1440 #endif /* __ALT_CLK_MGR_H__ */
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