include/bsp/alt_clock_group.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMCycVContrib
0005  */
0006
0007 /******************************************************************************
0008  *
0009  * Copyright 2013 Altera Corporation. All Rights Reserved.
0010  *
0011  * Redistribution and use in source and binary forms, with or without
0012  * modification, are permitted provided that the following conditions are met:
0013  *
0014  * 1. Redistributions of source code must retain the above copyright notice,
0015  * this list of conditions and the following disclaimer.
0016  *
0017  * 2. Redistributions in binary form must reproduce the above copyright notice,
0018  * this list of conditions and the following disclaimer in the documentation
0019  * and/or other materials provided with the distribution.
0020  *
0021  * 3. The name of the author may not be used to endorse or promote products
0022  * derived from this software without specific prior written permission.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
0025  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0026  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
0027  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0028  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
0029  * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0032  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
0033  * OF SUCH DAMAGE.
0034  *
0035  ******************************************************************************/
0036
0037 /*!
0038  * \file
0039  *
0040  * Contains the definition of an opaque data structure that contains raw
0041  * configuration information for a clock group.
0042  */
0043
0044 #ifndef __ALT_CLK_GRP_H__
0045 #define __ALT_CLK_GRP_H__
0046
0047 #include "hwlib.h"
0048 #include "socal/alt_clkmgr.h"
0049
0050 #ifdef __cplusplus
0051 extern "C"
0052 {
0053 #endif  /* __cplusplus */
0054
0055 /*!
0056  * This type definition enumerates the clock groups
0057  */
0058 typedef enum ALT_CLK_GRP_e
0059 {
0060     ALT_MAIN_PLL_CLK_GRP,        /*!< Main PLL clock group */
0061
0062     ALT_PERIPH_PLL_CLK_GRP,      /*!< Peripheral PLL clock group */
0063
0064     ALT_SDRAM_PLL_CLK_GRP        /*!< SDRAM PLL clock group */
0065
0066 } ALT_CLK_GRP_t;
0067
0068 /*!
0069  * This type definition defines an opaque data structure for holding the
0070  * configuration settings for a complete clock group.
0071  */
0072 typedef struct ALT_CLK_GROUP_RAW_CFG_s
0073 {
0074     uint32_t      verid;     /*!< SoC FPGA version identifier. This field
0075                               *   encapsulates the silicon identifier and
0076                               *   version information associated with this
0077                               *   clock group configuration. It is used to
0078                               *   assert that this clock group configuration
0079                               *   is valid for this device. */
0080
0081     uint32_t      siliid2;   /*!< Reserved register - reserved for future
0082                               *   device IDs or capability flags. */
0083
0084     ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */
0085
0086     /*!
0087      * This union holds the register values for configuration of the set of
0088      * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator
0089      * identifies the valid clock group union data member.
0090      */
0091     union ALT_CLK_GROUP_RAW_CFG_u
0092     {
0093         /*! Clock group configuration for Main PLL group. */
0094         union
0095         {
0096             ALT_CLKMGR_MAINPLL_t     fld; /*!< Field access. */
0097             ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */
0098         } mainpllgrp;
0099
0100         /*! Clock group configuration for Peripheral PLL group. */
0101         union
0102         {
0103             ALT_CLKMGR_PERPLL_t     fld; /*!< Field access. */
0104             ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */
0105         } perpllgrp;
0106
0107         /*! Clock group configuration for SDRAM PLL group. */
0108         union
0109         {
0110             ALT_CLKMGR_SDRPLL_t     fld; /*!< Field access. */
0111             ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */
0112         } sdrpllgrp;
0113
0114     } clkgrp;
0115 } ALT_CLK_GROUP_RAW_CFG_t;
0116
0117 #ifdef __cplusplus
0118 }
0119 #endif  /* __cplusplus */
0120 #endif  /* __ALT_CLK_GRP_H__ */