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0001 /** 0002 * @file 0003 * 0004 * @ingroup RTEMSBSPsARMCycVContrib 0005 */ 0006 0007 /*! \file 0008 * Altera - SoC FPGA Address Space Manager 0009 */ 0010 0011 /****************************************************************************** 0012 * 0013 * Copyright 2013 Altera Corporation. All Rights Reserved. 0014 * 0015 * Redistribution and use in source and binary forms, with or without 0016 * modification, are permitted provided that the following conditions are met: 0017 * 0018 * 1. Redistributions of source code must retain the above copyright notice, 0019 * this list of conditions and the following disclaimer. 0020 * 0021 * 2. Redistributions in binary form must reproduce the above copyright notice, 0022 * this list of conditions and the following disclaimer in the documentation 0023 * and/or other materials provided with the distribution. 0024 * 0025 * 3. The name of the author may not be used to endorse or promote products 0026 * derived from this software without specific prior written permission. 0027 * 0028 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR 0029 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 0030 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO 0031 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 0032 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 0033 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 0034 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 0035 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 0036 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 0037 * OF SUCH DAMAGE. 0038 * 0039 ******************************************************************************/ 0040 0041 #ifndef __ALT_ADDRESS_SPACE_H__ 0042 #define __ALT_ADDRESS_SPACE_H__ 0043 0044 #include <stdbool.h> 0045 #include "hwlib.h" 0046 #include "socal/hps.h" 0047 0048 #ifdef __cplusplus 0049 extern "C" 0050 { 0051 #endif /* __cplusplus */ 0052 0053 /******************************************************************************/ 0054 // ARM Level 2 Cache Controller L2C-310 Register Interface 0055 0056 // Address Filtering Start Register 0057 // The Address Filtering Start Register is a read and write register. 0058 // Bits Field Description 0059 // :-------|:--------------------------|:----------------------------------------- 0060 // [31:20] | address_filtering_start | Address filtering start address for 0061 // | | bits [31:20] of the filtering address. 0062 // [19:1] | Reserved | SBZ/RAZ 0063 // [0] | address_filtering_enable | 0 - address filtering disabled 0064 // | | 1 - address filtering enabled. 0065 0066 // Address Filtering Start Register Address 0067 #define L2_CACHE_ADDR_FILTERING_START_OFST 0xC00 0068 #define L2_CACHE_ADDR_FILTERING_START_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_START_OFST) 0069 // Address Filtering Start Register - Start Value Mask 0070 #define L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000 0071 // Address Filtering Start Register - Reset Start Address Value (1 MB) 0072 #define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000 0073 // Address Filtering Start Register - Enable Flag Mask 0074 #define L2_CACHE_ADDR_FILTERING_ENABLE_MASK 0x00000001 0075 // Address Filtering Start Register - Reset Enable Flag Value (Enabled) 0076 #define L2_CACHE_ADDR_FILTERING_ENABLE_RESET 0x1 0077 0078 // Address Filtering End Register 0079 // The Address Filtering End Register is a read and write register. 0080 // Bits Field Description 0081 // :-------|:--------------------------|:----------------------------------------- 0082 // [31:20] | address_filtering_end | Address filtering end address for bits 0083 // | | [31:20] of the filtering address. 0084 // [19:0] | Reserved | SBZ/RAZ 0085 0086 // Address Filtering End Register Address 0087 #define L2_CACHE_ADDR_FILTERING_END_OFST 0xC04 0088 #define L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST) 0089 // Address Filtering End Register - End Value Mask 0090 #define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000 0091 // Address Filtering End Register - Reset End Address Value (3 GiB) 0092 #define L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000 0093 0094 #ifndef __ASSEMBLY__ 0095 0096 /******************************************************************************/ 0097 /*! \addtogroup ADDR_SPACE_MGR The Address Space Manager 0098 * 0099 * This module contains group APIs for managing the HPS address space. This 0100 * module contains group APIs to manage: 0101 * * Memory Map Control 0102 * * Memory Coherence 0103 * * Cache Managment 0104 * * MMU Managment 0105 * 0106 * @{ 0107 */ 0108 0109 /******************************************************************************/ 0110 /*! \addtogroup ADDR_SPACE_MGR_REMAP Address Space Mapping Control 0111 * 0112 * This group API provides functions to map and remap selected address ranges 0113 * into the accessible (visible) views of the MPU and non MPU address spaces. 0114 * 0115 * \b Caveats 0116 * 0117 * \b NOTE: Caution should be observed when remapping address 0 to different 0118 * memory. The code performing the remapping operation should not be executing 0119 * in the address range being remapped to different memory. 0120 * 0121 * For example, if address 0 is presently mapped to OCRAM and the code is 0122 * preparing to remap address 0 to SDRAM, then the code must not be executing in 0123 * the range 0 to 64 KB as this address space is about to be remapped to 0124 * different memory. If the code performing the remap operation is executing 0125 * from OCRAM then it needs to be executing from its permanently mapped OCRAM 0126 * address range in upper memory (i.e. ALT_OCRAM_LB_ADDR to ALT_OCRAM_UB_ADDR). 0127 * 0128 * \b NOTE: The MPU address space view is controlled by two disparate hardware 0129 * control interfaces: the L3 remap register and the L2 cache address filtering 0130 * registers. To complicate matters, the L3 remap register is write-only which 0131 * means not only that current remap register state cannot be read but also that 0132 * a read-modify-write operation cannot be performed on the register. 0133 * 0134 * This should not present a problem in most use case scenarios except for the 0135 * case where a current MPU address space mapping of 0 to SDRAM is being changed 0136 * to to a mapping of 0 to Boot ROM or OCRAM. 0137 * 0138 * In this case, a two step process whereby the L3 remap register is first set 0139 * to the new desired MPU address 0 mapping and then the L2 cache address 0140 * filtering registers have their address ranges adjusted accordingly must be 0141 * followed. An example follows: 0142 \verbatim 0143 // 1 MB reset default value for address filtering start 0144 #define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000 0145 uint32_t addr_filt_start; 0146 uint32_t addr_filt_end; 0147 0148 // Perform L3 remap register programming first by setting the desired new MPU 0149 // address space 0 mapping. Assume OCRAM for the example. 0150 alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM, ...); 0151 0152 // Next, adjust the L2 cache address filtering range. Set the start address to 0153 // the default reset value and retain the existing end address configuration. 0154 alt_l2_addr_filter_cfg_get(&addr_filt_start, &addr_filt_end); 0155 if (addr_filt_start != L2_CACHE_ADDR_FILTERING_START_RESET) 0156 { 0157 alt_l2_addr_filter_cfg_set(L2_CACHE_ADDR_FILTERING_START_RESET, addr_filt_end); 0158 } 0159 \endverbatim 0160 * @{ 0161 */ 0162 0163 /******************************************************************************/ 0164 /*! 0165 * This type definition enumerates the MPU address space attributes. 0166 * 0167 * The MPU address space consists of the ARM Cortex A9 processors and associated 0168 * processor peripherals (cache, MMU). 0169 */ 0170 typedef enum ALT_ADDR_SPACE_MPU_ATTR_e 0171 { 0172 ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM, /*!< Maps the Boot ROM to address 0173 * 0x0 for the MPU L3 master. Note 0174 * that the Boot ROM is also 0175 * always mapped to address 0176 * 0xfffd_0000 for the MPU L3 0177 * master independent of 0178 * attribute. 0179 */ 0180 0181 ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address 0182 * 0x0 for the MPU L3 master. Note 0183 * that the On-chip RAM is also 0184 * always mapped to address 0185 * 0xffff_0000 for the MPU L3 0186 * master independent of this 0187 * attribute. 0188 */ 0189 } ALT_ADDR_SPACE_MPU_ATTR_t; 0190 0191 /******************************************************************************/ 0192 /*! 0193 * This type definition enumerates the non-MPU address space attributes. 0194 * 0195 * The non-MPU address space consists of the non-MPU L3 masters including the 0196 * DMA controllers (standalone and those built into peripherals), the F2H AXI 0197 * Bridge, and the DAP. 0198 */ 0199 typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e 0200 { 0201 ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM, /*!< Maps the SDRAM to address 0x0 0202 * for the non-MPU L3 masters. 0203 */ 0204 ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address 0205 * 0x0 for the non-MPU L3 0206 * masters. Note that the On-chip 0207 * RAM is also always mapped to 0208 * address 0xffff_0000 for the 0209 * non-MPU L3 masters independent 0210 * of this attribute. 0211 */ 0212 } ALT_ADDR_SPACE_NONMPU_ATTR_t; 0213 0214 /******************************************************************************/ 0215 /*! 0216 * This type definition enumerates the HPS to FPGA bridge accessiblity 0217 * attributes. 0218 */ 0219 typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e 0220 { 0221 ALT_ADDR_SPACE_H2F_INACCESSIBLE, /*!< The H2F AXI Bridge is not 0222 * visible to L3 masters. Accesses 0223 * to the associated address range 0224 * return an AXI decode error to 0225 * the master. 0226 */ 0227 ALT_ADDR_SPACE_H2F_ACCESSIBLE /*!< The H2F AXI Bridge is visible 0228 * to L3 masters. 0229 */ 0230 } ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t; 0231 0232 /******************************************************************************/ 0233 /*! 0234 * This type definition enumerates the Lightweight HPS to FPGA bridge 0235 * accessiblity attributes. 0236 */ 0237 typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e 0238 { 0239 ALT_ADDR_SPACE_LWH2F_INACCESSIBLE, /*!< The LWH2F AXI Bridge is not 0240 * visible to L3 masters. Accesses 0241 * to the associated address range 0242 * return an AXI decode error to 0243 * the master. 0244 */ 0245 ALT_ADDR_SPACE_LWH2F_ACCESSIBLE /*!< The LWH2F AXI Bridge is visible 0246 * to L3 masters. 0247 */ 0248 } ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t; 0249 0250 /******************************************************************************/ 0251 /*! 0252 * Configures the mapped and accessible (visible) address ranges for the HPS 0253 * MPU, non-MPU, and Bridge address spaces. 0254 * 0255 * \param mpu_attr 0256 * The MPU address space configuration attributes. 0257 * 0258 * \param nonmpu_attr 0259 * The non-MPU address space configuration attributes. 0260 * 0261 * \param h2f_attr 0262 * The H2F Bridge attribute mapping and accessibility attributes. 0263 * 0264 * \param lwh2f_attr 0265 * The Lightweight H2F Bridge attribute mapping and accessibility 0266 * attributes. 0267 * 0268 * 0269 * \retval ALT_E_SUCCESS The operation was succesful. 0270 * \retval ALT_E_ERROR The operation failed. 0271 * \retval ALT_E_INV_OPTION One or more invalid attribute options were 0272 * specified. 0273 */ 0274 ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr, 0275 ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr, 0276 ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_attr, 0277 ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_attr); 0278 0279 /******************************************************************************/ 0280 /*! 0281 * Maps SDRAM to address 0x0 for the MPU address space view. 0282 * 0283 * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest 0284 * 64KB of the boot region are accessible because the size of the Boot ROM and 0285 * on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MiB) to 0286 * 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to 0287 * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not 0288 * accessible to the MPU unless address 0 is remapped to SDRAM after reset. 0289 * 0290 * This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access 0291 * SDRAM. 0292 * 0293 * \internal 0294 * The remap to address 0x0 is achieved by configuring the L2 cache Address 0295 * Filtering Registers to redirect address 0x0 to \e sdram_end_addr to the SDRAM 0296 * AXI (M1) master port by calling: 0297 * 0298 * alt_l2_addr_filter_cfg_set(0x0, <current_addr_filt_end_value>); 0299 * 0300 * See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical 0301 * Reference Manual, Section 3.3.12 Address Filtering </em>. 0302 * \endinternal 0303 * 0304 * \retval ALT_E_SUCCESS The operation was succesful. 0305 * \retval ALT_E_ERROR The operation failed. 0306 */ 0307 ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void); 0308 0309 /*! @} */ 0310 0311 /******************************************************************************/ 0312 /*! \addtogroup L2_ADDR_FLTR L2 Cache Address Filter 0313 * 0314 * The L2 cache address filter controls where physical addresses within certain 0315 * ranges of the MPU address space are directed. 0316 * 0317 * The L2 cache has master port connections to the L3 interconnect and the SDRAM 0318 * controller. A programmable address filter controls which portions of the 0319 * 32-bit physical address space use each master. 0320 * 0321 * When l2 address filtering is configured and enabled, a physical address will 0322 * be redirected to one master or the other based upon the address filter 0323 * configuration. 0324 * 0325 * If \b address_filter_start <= \e physical_address < \b address_filter_end: 0326 * * then redirect \e physical_address to AXI Master Port M1 (SDRAM controller) 0327 * * else redirect \e physical_address to AXI Master Port M0 (L3 interconnect) 0328 * 0329 * See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical 0330 * Reference Manual, Section 3.3.12 Address Filtering </em> for more information. 0331 * @{ 0332 */ 0333 0334 /******************************************************************************/ 0335 /*! 0336 * Get the L2 cache address filtering configuration settings. 0337 * 0338 * \param addr_filt_start 0339 * [out] An output parameter variable for the address filtering 0340 * start address for the range of physical addresses redirected to 0341 * the SDRAM AXI master port. The value returned is always a 1 MiB 0342 * aligned address. 0343 * 0344 * \param addr_filt_end 0345 * [out] An output parameter variable for the address filtering 0346 * end address for the range of physical addresses redirected to 0347 * the SDRAM AXI master port. The value returned is always a 1 MiB 0348 * aligned address. 0349 * 0350 * \retval ALT_E_SUCCESS The operation was successful. 0351 * \retval ALT_E_ERROR The operation failed. 0352 * \retval ALT_E_BAD_ARG An bad argument was passed. Either \e addr_filt_start 0353 * or \e addr_filt_end or both are invalid addresses. 0354 */ 0355 ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start, 0356 uint32_t* addr_filt_end); 0357 0358 /******************************************************************************/ 0359 /*! 0360 * Set the L2 cache address filtering configuration settings. 0361 * 0362 * Address filtering start and end values must be 1 MiB aligned. 0363 * 0364 * \param addr_filt_start 0365 * The address filtering start address for the range of physical 0366 * addresses redirected to the SDRAM AXI master port. Only bits 0367 * [31:20] of the address are valid. Any bits outside the range 0368 * [31:20] are invalid and will cause an error status to be 0369 * returned. 0370 * 0371 * \param addr_filt_end 0372 * The address filtering end address for the range of physical 0373 * addresses redirected to the SDRAM AXI master port. Only bits 0374 * [31:20] of the address are valid. Any bits outside the range 0375 * [31:20] are invalid and will cause an error status to be 0376 * returned. 0377 * 0378 * \retval ALT_E_SUCCESS The operation was succesful. 0379 * \retval ALT_E_ERROR The operation failed. 0380 * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or 0381 * more address arguments do not satisfy the argument 0382 * constraints. 0383 */ 0384 ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start, 0385 uint32_t addr_filt_end); 0386 0387 /*! @} */ 0388 0389 /******************************************************************************/ 0390 /*! \addtogroup ADDR_SPACE_MGR_MEM_COHERENCE ACP Memory Coherence and ID Mapping 0391 * 0392 * This API provides management of the ACP ID Mapper that enables data coherent 0393 * access to the MPU address space by external masters. The set of external 0394 * masters include L3 master peripherals and FPGA soft IP. 0395 * 0396 * The Accelerator Coherency Port (ACP) allows peripherals - including FPGA 0397 * based soft IP - to maintain data coherency with the Cortex-A9 MPCore 0398 * processors and the Snoop Control Unit (SCU). 0399 * 0400 * The ACP supports up to six masters. However, soft IP implemented in the FPGA 0401 * fabric can have a larger number of masters that need to access the ACP. The 0402 * ACP ID Mapper expands the number of masters able to access the ACP. The ACP 0403 * ID Mapper is situated between the interconnect and the ACP of the MPU 0404 * subsystem. It has the following characteristics: 0405 * * Support for up to six concurrent ID mappings. 0406 * * 1 GiB coherent window into 4 GiB MPU address space 0407 * * Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU) 0408 * and L2 cache. 0409 * 0410 * The function of the ACP ID Mapper is to map 12-bit Advanced Microcontroller 0411 * Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) IDs (input 0412 * identifiers) from the Level 3 (L3) interconnect to 3-bit AXI IDs (output 0413 * identifiers) required by the ACP slave port. 0414 * 0415 * The ACP ID Mapper supports the two ID mapping modes: 0416 * * Dynamic Mapping - In this mode an input ID is automatically mapped to an 0417 * available output ID. The dynamic mode is more flexible because the hardware 0418 * handles the mapping. The hardware mapping allows an output ID to be used 0419 * for more than one input ID. Output IDs are assigned to input IDs on a 0420 * first-come, first-served basis. 0421 * * Fixed Mapping - In this mode there is a one-to-one mapping from input IDs 0422 * to output IDs. 0423 * 0424 * Out of the total of eight ACP output ID values, only six are available to the 0425 * ACP ID Mapper for remapping. The first two output IDs (0 and 1) are 0426 * dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the 0427 * last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6 0428 * support fixed and dynamic modes of operation while output ID 7 supports 0429 * dynamic mode only. 0430 * 0431 * The following table summarizes the usage of the 3-bit ouput ID values by the 0432 * ACP ID Mapper and their settings at reset. 0433 * 0434 * Output ID | Usage | Reset State 0435 * :-----------|:--------------------------------------------------|:------------ 0436 * 0 | Reserved for Cortex-A9 cores. | - 0437 * 1 | Reserved for Cortex-A9 cores. | - 0438 * 2 | Assigned to Debug Access Port (DAP) input ID at | Fixed 0439 * : | reset. After reset, can be reconfigured to either | DAP Master 0440 * : | fixed or dynamic. |: 0441 * 3 | Configurable fixed or dynamic mode. | Dynamic 0442 * 4 | Configurable fixed or dynamic mode. | Dynamic 0443 * 5 | Configurable fixed or dynamic mode. | Dynamic 0444 * 6 | Configurable fixed or dynamic mode. | Dynamic 0445 * 7 | Dynamic mode only. | Dynamic 0446 * 0447 * Where <em>Output ID</em> is the ACP ID Mapper output value that goes to the ACP. 0448 * 0449 * Additionally, for masters unable to drive the AXI user sideband signals of 0450 * incoming transactions, the ACP ID Mapper allows control of the AXI user 0451 * sideband signal values. Not all masters drive these signals, so the ACP ID 0452 * Mapper makes it possible to drive the 5-bit user sideband signal with either 0453 * a default value (in dynamic mode) or specific values (in fixed mode). 0454 * 0455 * The ACP ID Mapper can also control which 1 GiB coherent window into memory is 0456 * accessed by masters of the L3 interconnect. Each fixed mapping can be 0457 * assigned a different user sideband signal and memory window to allow specific 0458 * settings for different masters. All dynamic mappings share a common user 0459 * sideband signal and memory window setting. One important exception, however, 0460 * is that the ACP ID mapper always allows user sideband signals from the 0461 * FPGA-to-HPS bridge to pass through to the ACP regardless of the configured 0462 * user sideband value associated with the ID. 0463 * 0464 * The ACP ID Mapper has a 1 GiB address window into the MPU address space, which 0465 * is by default a view into the bottom 1 GiB of SDRAM. The ACP ID Mapper allows 0466 * transactions to be routed to different 1 GiB-sized memory views, called pages, 0467 * in both dynamic and fixed modes. 0468 * 0469 * See: <em>Chapter 6: Cortex-A9 Microprocessor Unit Subsystem</em> in 0470 * <em>Volume 3: Hard Processor System Technical Reference Manual</em> of the 0471 * <em>Arria V or Cyclone V Device Handbook</em> for a complete discussion of 0472 * the operation and restrictions on the ACP and the ACP ID Mapper. 0473 * 0474 * @{ 0475 */ 0476 0477 /******************************************************************************/ 0478 /*! 0479 * \name External Master ID Macros 0480 * 0481 * These macros define the HPS external master identifiers that are 12-bit input 0482 * IDs to the ACP ID Mapper. Some of the masters have a range of identifier 0483 * values assigned to them and are distinguished by taking a <em>(var)\</em> 0484 * argument. 0485 * @{ 0486 */ 0487 0488 /*! Bit mask for the relevant 12 bits of an external master ID */ 0489 #define ALT_ACP_ID_MAP_MASTER_ID_MASK 0xfff 0490 0491 /*! Master ID for L2M0 */ 0492 #define ALT_ACP_ID_MAP_MASTER_ID_L2M0(var) (0x00000002 | (0x000007f8 & (var))) 0493 /*! Master ID for DMA */ 0494 #define ALT_ACP_ID_MAP_MASTER_ID_DMA(var) (0x00000001 | (0x00000078 & (var))) 0495 /*! Master ID for EMAC0 */ 0496 #define ALT_ACP_ID_MAP_MASTER_ID_EMAC0(var) (0x00000801 | (0x00000878 & (var))) 0497 /*! Master ID for EMAC1 */ 0498 #define ALT_ACP_ID_MAP_MASTER_ID_EMAC1(var) (0x00000802 | (0x00000878 & (var))) 0499 /*! Master ID for USB0 */ 0500 #define ALT_ACP_ID_MAP_MASTER_ID_USB0 0x00000803 0501 /*! Master ID for USB1 */ 0502 #define ALT_ACP_ID_MAP_MASTER_ID_USB1 0x00000806 0503 /*! Master ID for NAND controller */ 0504 #define ALT_ACP_ID_MAP_MASTER_ID_NAND(var) (0x00000804 | (0x00000ff8 & (var))) 0505 /*! Master ID for Embedded Trace Router (ETR) */ 0506 #define ALT_ACP_ID_MAP_MASTER_ID_TMC 0x00000800 0507 /*! Master ID for Debug Access Port (DAP) */ 0508 #define ALT_ACP_ID_MAP_MASTER_ID_DAP 0x00000004 0509 /*! Master ID for SD/MMC controller */ 0510 #define ALT_ACP_ID_MAP_MASTER_ID_SDMMC 0x00000805 0511 /*! Master ID for FPGA to HPS (F2H) bridge - conduit for soft IP masters in FPGA fabric */ 0512 #define ALT_ACP_ID_MAP_MASTER_ID_F2H(var) (0x00000000 | (0x000007f8 & (var))) 0513 /*! @} */ 0514 0515 /******************************************************************************/ 0516 /*! 0517 * This type defines the enumerations 3-bit output ids to ACP ID mapper. 0518 */ 0519 typedef enum ALT_ACP_ID_OUTPUT_ID_e 0520 { 0521 ALT_ACP_ID_OUT_FIXED_ID_2 = 2, /*!< Assigned to the input ID of the DAP at reset. 0522 * After reset, can be either fixed or dynamic, 0523 * programmed by software. 0524 */ 0525 ALT_ACP_ID_OUT_DYNAM_ID_3 = 3, /*!< Fixed or dynamic, programmed by software output id */ 0526 ALT_ACP_ID_OUT_DYNAM_ID_4 = 4, /*!< Fixed or dynamic, programmed by software output id */ 0527 ALT_ACP_ID_OUT_DYNAM_ID_5 = 5, /*!< Fixed or dynamic, programmed by software output id */ 0528 ALT_ACP_ID_OUT_DYNAM_ID_6 = 6, /*!< Fixed or dynamic, programmed by software output id */ 0529 ALT_ACP_ID_OUT_DYNAM_ID_7 = 7 /*!< Dynamic mapping only */ 0530 } ALT_ACP_ID_OUTPUT_ID_t; 0531 0532 /*! 0533 * This type defines the enumerations used to specify the 1 GiB page view of the 0534 * MPU address space used by an ACP ID mapping configuration. 0535 */ 0536 typedef enum ALT_ACP_ID_MAP_PAGE_e 0537 { 0538 ALT_ACP_ID_MAP_PAGE_0 = 0, /*!< Page 0 - MPU address range 0x00000000 - 0x3FFFFFFF */ 0539 ALT_ACP_ID_MAP_PAGE_1 = 1, /*!< Page 1 - MPU address range 0x40000000 - 0x7FFFFFFF */ 0540 ALT_ACP_ID_MAP_PAGE_2 = 2, /*!< Page 2 - MPU address range 0x80000000 - 0xBFFFFFFF */ 0541 ALT_ACP_ID_MAP_PAGE_3 = 3 /*!< Page 3 - MPU address range 0xC0000000 - 0xFFFFFFFF */ 0542 } ALT_ACP_ID_MAP_PAGE_t; 0543 0544 /******************************************************************************/ 0545 /*! 0546 * Configure a fixed ACP ID mapping for read transactions originating from 0547 * external masters identified by \e input_id. The \e input_id value is 0548 * translated to the specified 3-bit \e output_id required by the ACP slave 0549 * port. 0550 * 0551 * \param input_id 0552 * The 12 bit external master ID originating read transactions 0553 * targeted for ID translation. Valid argument range must be 0 <= 0554 * \e output_id <= 4095. 0555 * 0556 * \param output_id 0557 * The 3-bit output ID value the ACP ID Mapper translates read 0558 * transactions identified by \e input_id to. This is the value 0559 * propogated to the ACP slave port. Valid argument values must be 0560 * 0 <= \e output_id <= 7. 0561 * 0562 * \param page 0563 * The MPU address space page view to use for the ACP window used 0564 * by the ID tranlation mapping. 0565 * 0566 * \param aruser 0567 * The 5-bit AXI ARUSER read user sideband signal value to use for 0568 * masters unable to drive the AXI user sideband signals. Valid 0569 * argument range is 0 <= \e aruser <= 31. 0570 * 0571 * \retval ALT_E_SUCCESS The operation was succesful. 0572 * \retval ALT_E_ERROR The operation failed. 0573 * \retval ALT_E_RESERVED The argument value is reserved or unavailable. 0574 * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or 0575 * more of the \e input_id, and/or \e output_id 0576 * arguments violates its range constraint. 0577 * \retval ALT_E_BAD_ARG The \e page argument is invalid. 0578 */ 0579 ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id, 0580 const uint32_t output_id, 0581 const ALT_ACP_ID_MAP_PAGE_t page, 0582 const uint32_t aruser); 0583 0584 /******************************************************************************/ 0585 /*! 0586 * Configure a fixed ACP ID mapping for write transactions originating from 0587 * external masters identified by \e input_id. The \e input_id value is 0588 * translated to the specified 3-bit \e output_id required by the ACP slave 0589 * port. 0590 * 0591 * \param input_id 0592 * The 12 bit external master ID originating write transactions 0593 * targeted for ID translation. Valid argument range must be 0 <= 0594 * \e output_id <= 4095. 0595 * 0596 * \param output_id 0597 * The 3-bit output ID value the ACP ID Mapper translates write 0598 * transactions identified by \e input_id to. This is the value 0599 * propogated to the ACP slave port. Valid argument values must be 0600 * 0 <= \e output_id <= 7. 0601 * 0602 * \param page 0603 * The MPU address space page view to use for the ACP window used 0604 * by the ID tranlation mapping. 0605 * 0606 * \param awuser 0607 * The 5-bit AXI AWUSER write user sideband signal value to use for 0608 * masters unable to drive the AXI user sideband signals. Valid 0609 * argument range is 0 <= \e awuser <= 31. 0610 * 0611 * \retval ALT_E_SUCCESS The operation was succesful. 0612 * \retval ALT_E_ERROR The operation failed. 0613 * \retval ALT_E_RESERVED The argument value is reserved or unavailable. 0614 * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or 0615 * more of the \e input_id, and/or \e output_id 0616 * arguments violates its range constraint. 0617 * \retval ALT_E_BAD_ARG The \e page argument is invalid. 0618 */ 0619 ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id, 0620 const uint32_t output_id, 0621 const ALT_ACP_ID_MAP_PAGE_t page, 0622 const uint32_t awuser); 0623 0624 /******************************************************************************/ 0625 /*! 0626 * Configure the designated 3-bit output ID as an available identifier resource 0627 * for use by the dynamic ID mapping function of the ACP ID Mapper for read 0628 * transactions. The \e output_id value is available for dynamic assignment to 0629 * external master read transaction IDs that do not have an explicit fixed ID 0630 * mapping. 0631 * 0632 * \param output_id 0633 * The 3-bit output ID value designated as an available ID for use 0634 * by the dynamic mapping function of the ACP ID Mapper. The \e 0635 * ouput_id value is used exclusively for dynamic ID mapping until 0636 * reconfigured as a fixed ID mapping by a call to 0637 * alt_acp_id_map_fixed_read_set(). Valid argument values must be 0638 * 0 <= \e output_id <= 7. 0639 * 0640 * \retval ALT_E_SUCCESS The operation was succesful. 0641 * \retval ALT_E_ERROR The operation failed. 0642 * \retval ALT_E_RESERVED The argument value is reserved or unavailable. 0643 * \retval ALT_E_ARG_RANGE An argument violates a range constraint. 0644 */ 0645 ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id); 0646 0647 /******************************************************************************/ 0648 /*! 0649 * Configure the designated 3-bit output ID as an available identifier resource 0650 * for use by the dynamic ID mapping function of the ACP ID Mapper for write 0651 * transactions. The \e output_id value is available for dynamic assignment to 0652 * external master write transaction IDs that do not have an explicit fixed ID 0653 * mapping. 0654 * 0655 * \param output_id 0656 * The 3-bit output ID value designated as an available ID for use 0657 * by the dynamic mapping function of the ACP ID Mapper. The \e 0658 * ouput_id value is used exclusively for dynamic ID mapping until 0659 * reconfigured as a fixed ID mapping by a call to 0660 * alt_acp_id_map_fixed_write_set(). Valid argument values must be 0661 * 0 <= \e output_id <= 7. 0662 * 0663 * \retval ALT_E_SUCCESS The operation was succesful. 0664 * \retval ALT_E_ERROR The operation failed. 0665 * \retval ALT_E_RESERVED The argument value is reserved or unavailable. 0666 * \retval ALT_E_ARG_RANGE An argument violates a range constraint. 0667 */ 0668 ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id); 0669 0670 /******************************************************************************/ 0671 /*! 0672 * Configure the page and user read sideband signal options that are applied to 0673 * all read transactions that have their input IDs dynamically mapped. 0674 * 0675 * \param page 0676 * The MPU address space page view to use for the ACP window used 0677 * by the dynamic ID tranlation mapping. 0678 * 0679 * \param aruser 0680 * The 5-bit AXI ARUSER read user sideband signal value to use for 0681 * masters unable to drive the AXI user sideband signals. Valid 0682 * argument range is 0 <= \e aruser <= 31. 0683 * 0684 * \retval ALT_E_SUCCESS The operation was succesful. 0685 * \retval ALT_E_ERROR The operation failed. 0686 * \retval ALT_E_RESERVED The argument value is reserved or unavailable. 0687 * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or 0688 * more of the \e page and/or \e aruser 0689 * arguments violates its range constraint. 0690 * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master 0691 * identifier. 0692 */ 0693 ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page, 0694 const uint32_t aruser); 0695 0696 /******************************************************************************/ 0697 /*! 0698 * Configure the page and user write sideband signal options that are applied to 0699 * all write transactions that have their input IDs dynamically mapped. 0700 * 0701 * \param page 0702 * The MPU address space page view to use for the ACP window used 0703 * by the dynamic ID tranlation mapping. 0704 * 0705 * \param awuser 0706 * The 5-bit AXI AWUSER write user sideband signal value to use for 0707 * masters unable to drive the AXI user sideband signals. Valid 0708 * argument range is 0 <= \e aruser <= 31. 0709 * 0710 * \retval ALT_E_SUCCESS The operation was succesful. 0711 * \retval ALT_E_ERROR The operation failed. 0712 * \retval ALT_E_RESERVED The argument value is reserved or unavailable. 0713 * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or 0714 * more of the \e page and/or \e awuser 0715 * arguments violates its range constraint. 0716 * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master 0717 * identifier. 0718 */ 0719 ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page, 0720 const uint32_t awuser); 0721 0722 /******************************************************************************/ 0723 /*! 0724 * Return the current read transaction mapping configuration used by the ACP ID 0725 * Mapper for the specified output ID. 0726 * 0727 * If \e output_id is configured as a fixed mapping then \b true is returned in 0728 * the \e fixed output parameter and the translation mapping options configured 0729 * for that \e output_id are returned in the other output parameters. 0730 * 0731 * If \e output_id is configured as a dynamic mapping then \b false is returned 0732 * in the \e fixed output parameter and the translation mapping options 0733 * configured for all dynamically remapped output IDs are returned in the other 0734 * output parameters. 0735 * 0736 * \param output_id 0737 * The output ID to return the mapping configuration for. 0 <= \e 0738 * output_id <= 7. 0739 * 0740 * \param fixed 0741 * [out] Set to \b true if the specified \e output_id is a fixed ID 0742 * mapping configuration. Set to \b false if the mapping 0743 * configuration is dynamic. 0744 * 0745 * \param input_id 0746 * [out] The input ID of the external master that a fixed ID 0747 * mapping is applied to for the \e output_id. If \e fixed is \b 0748 * false then this output parameter is set to 0 and its value 0749 * should be considered as not applicable. 0750 * 0751 * \param page 0752 * [out] The MPU address space page view used by the mapping 0753 * configuration. 0754 * 0755 * \param aruser 0756 * [out] The 5-bit AXI ARUSER read user sideband signal value used 0757 * by the mapping configuration when masters are unable to drive 0758 * the AXI user sideband signals. 0759 * 0760 * \retval ALT_E_SUCCESS The operation was succesful. 0761 * \retval ALT_E_ERROR The operation failed. 0762 * \retval ALT_E_RESERVED The argument value is reserved or unavailable. 0763 * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e 0764 * output_id argument violates its range constraint. 0765 */ 0766 ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id, 0767 bool* fixed, 0768 uint32_t* input_id, 0769 ALT_ACP_ID_MAP_PAGE_t* page, 0770 uint32_t* aruser); 0771 0772 /******************************************************************************/ 0773 /*! 0774 * Return the current write transaction mapping configuration used by the ACP ID 0775 * Mapper for the specified output ID. 0776 * 0777 * If \e output_id is configured as a fixed mapping then \b true is returned in 0778 * the \e fixed output parameter and the translation mapping options configured 0779 * for that \e output_id are returned in the other output parameters. 0780 * 0781 * If \e output_id is configured as a dynamic mapping then \b false is returned 0782 * in the \e fixed output parameter and the translation mapping options 0783 * configured for all dynamically remapped output IDs are returned in the other 0784 * output parameters. 0785 * 0786 * \param output_id 0787 * The output ID to return the mapping configuration for. 0 <= \e 0788 * output_id <= 7. 0789 * 0790 * \param fixed 0791 * [out] Set to \b true if the specified \e output_id is a fixed ID 0792 * mapping configuration. Set to \b false if the mapping 0793 * configuration is dynamic. 0794 * 0795 * \param input_id 0796 * [out] The input ID of the external master that a fixed ID 0797 * mapping is applied to for the \e output_id. If \e fixed is \b 0798 * false then this output parameter is set to 0 and its value 0799 * should be considered as not applicable. 0800 * 0801 * \param page 0802 * [out] The MPU address space page view used by the mapping 0803 * configuration. 0804 * 0805 * \param awuser 0806 * [out] The 5-bit AXI AWUSER write user sideband signal value used 0807 * by the mapping configuration when masters are unable to drive 0808 * the AXI user sideband signals. 0809 * 0810 * \retval ALT_E_SUCCESS The operation was succesful. 0811 * \retval ALT_E_ERROR The operation failed. 0812 * \retval ALT_E_RESERVED The argument value is reserved or unavailable. 0813 * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e 0814 * output_id argument violates its range constraint. 0815 */ 0816 ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id, 0817 bool* fixed, 0818 uint32_t* input_id, 0819 ALT_ACP_ID_MAP_PAGE_t* page, 0820 uint32_t* awuser); 0821 0822 /*! @} */ 0823 0824 /*! @} */ 0825 0826 #endif /* __ASSEMBLY__ */ 0827 0828 #ifdef __cplusplus 0829 } 0830 #endif /* __cplusplus */ 0831 #endif /* __ALT_ADDRESS_SPACE_H__ */
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