altera-cyclone-v/include/bsp.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMCycV
0007  */
0008
0009 /*
0010  * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 #ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H
0035 #define LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H
0036
0037 /**
0038  * @defgroup RTEMSBSPsARMCycV Intel Cyclone V
0039  *
0040  * @ingroup RTEMSBSPsARM
0041  *
0042  * @brief Intel Cyclone V Board Support Package.
0043  *
0044  * @{
0045  */
0046
0047 #include <bspopts.h>
0048
0049 #define BSP_FEATURE_IRQ_EXTENSION
0050
0051 #ifndef ASM
0052
0053 #include <rtems.h>
0054
0055 #include <bsp/default-initial-extension.h>
0056
0057 #ifdef __cplusplus
0058 extern "C" {
0059 #endif /* __cplusplus */
0060
0061 #define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000
0062
0063 #define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 )
0064
0065 #define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 )
0066
0067 #define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
0068
0069 #ifndef BSP_ARM_A9MPCORE_PERIPHCLK
0070 extern uint32_t altera_cyclone_v_a9mpcore_periphclk;
0071 #define BSP_ARM_A9MPCORE_PERIPHCLK altera_cyclone_v_a9mpcore_periphclk
0072 #define ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK
0073 #endif
0074
0075 #define BSP_ARM_L2C_310_BASE 0xfffef000
0076
0077 #define BSP_ARM_L2C_310_ID 0x410000c9
0078
0079 #ifdef __cplusplus
0080 }
0081 #endif /* __cplusplus */
0082
0083 #endif /* ASM */
0084
0085 /* @} */
0086
0087 #endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H */