src/hwmgr/alt_reset_manager.c

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMCycVContrib
0005  */
0006
0007
0008 /******************************************************************************
0009 *
0010 * alt_reset_manager.c - API for the Altera SoC FPGA reset manager.
0011 *
0012 ******************************************************************************/
0013
0014 /******************************************************************************
0015 *
0016 * Copyright 2013 Altera Corporation. All Rights Reserved.
0017 *
0018 * Redistribution and use in source and binary forms, with or without
0019 * modification, are permitted provided that the following conditions are met:
0020 *
0021 * 1. Redistributions of source code must retain the above copyright notice,
0022 * this list of conditions and the following disclaimer.
0023 *
0024 * 2. Redistributions in binary form must reproduce the above copyright notice,
0025 * this list of conditions and the following disclaimer in the documentation
0026 * and/or other materials provided with the distribution.
0027 *
0028 * 3. The name of the author may not be used to endorse or promote products
0029 * derived from this software without specific prior written permission.
0030 *
0031 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
0032 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0033 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
0034 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0035 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
0036 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0037 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0038 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0039 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
0040 * OF SUCH DAMAGE.
0041 *
0042 ******************************************************************************/
0043
0044 #include <bsp/alt_reset_manager.h>
0045 #include <bsp/socal/socal.h>
0046 #include <bsp/socal/hps.h>
0047 #include <bsp/socal/alt_rstmgr.h>
0048
0049 /////
0050
0051
0052 uint32_t alt_reset_event_get(void)
0053 {
0054     return alt_read_word(ALT_RSTMGR_STAT_ADDR);
0055 }
0056
0057 ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask)
0058 {
0059     alt_write_word(ALT_RSTMGR_STAT_ADDR, event_mask);
0060     return ALT_E_SUCCESS;
0061 }
0062
0063 ALT_STATUS_CODE alt_reset_cold_reset(void)
0064 {
0065     alt_write_word(ALT_RSTMGR_CTL_ADDR, ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK);
0066     return ALT_E_SUCCESS;
0067 }
0068
0069 ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay,
0070                                      uint32_t nRST_pin_clk_assertion,
0071                                      bool sdram_refresh_enable,
0072                                      bool fpga_mgr_handshake,
0073                                      bool scan_mgr_handshake,
0074                                      bool fpga_handshake,
0075                                      bool etr_stall)
0076 {
0077     // Cached register values
0078     uint32_t ctrl_reg   = ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK;
0079     uint32_t counts_reg = 0;
0080
0081     /////
0082
0083     // Validate warm_reset_delay is above 16 and below the field width
0084     if ((warm_reset_delay < 16) || (warm_reset_delay >= (1 << ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH)))
0085     {
0086         return ALT_E_BAD_ARG;
0087     }
0088
0089     // Validate nRST_pin_clk_assertion delay is non-zero and below the field width
0090     if (!nRST_pin_clk_assertion)
0091     {
0092         return ALT_E_ERROR;
0093     }
0094     if (nRST_pin_clk_assertion >= (1 << ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH))
0095     {
0096         return ALT_E_BAD_ARG;
0097     }
0098
0099     // Update counts register with warm_reset_delay information
0100     counts_reg |= ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(warm_reset_delay);
0101
0102     // Update counts register with nRST_pin_clk_assertion information
0103     counts_reg |= ALT_RSTMGR_COUNTS_NRSTCNT_SET(nRST_pin_clk_assertion);
0104
0105     /////
0106
0107     // Update ctrl register with the specified option flags
0108
0109     if (sdram_refresh_enable)
0110     {
0111         ctrl_reg |= ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK;
0112     }
0113
0114     if (fpga_mgr_handshake)
0115     {
0116         ctrl_reg |= ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK;
0117     }
0118
0119     if (scan_mgr_handshake)
0120     {
0121         ctrl_reg |= ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK;
0122     }
0123
0124     if (fpga_handshake)
0125     {
0126         ctrl_reg |= ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK;
0127     }
0128
0129     if (etr_stall)
0130     {
0131         ctrl_reg |= ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK;
0132     }
0133
0134     /////
0135
0136     // Commit registers to hardware
0137     alt_write_word(ALT_RSTMGR_COUNTS_ADDR, counts_reg);
0138     alt_write_word(ALT_RSTMGR_CTL_ADDR,    ctrl_reg);
0139
0140     return ALT_E_SUCCESS;
0141 }