src/hwmgr/alt_address_space.c

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMCycVContrib
0005  */
0006
0007 /******************************************************************************
0008  *
0009  * alt_address_space.c - API for the Altera SoC FPGA address space.
0010  *
0011  ******************************************************************************/
0012
0013 /******************************************************************************
0014  *
0015  * Copyright 2013 Altera Corporation. All Rights Reserved.
0016  *
0017  * Redistribution and use in source and binary forms, with or without
0018  * modification, are permitted provided that the following conditions are met:
0019  *
0020  * 1. Redistributions of source code must retain the above copyright notice,
0021  * this list of conditions and the following disclaimer.
0022  *
0023  * 2. Redistributions in binary form must reproduce the above copyright notice,
0024  * this list of conditions and the following disclaimer in the documentation
0025  * and/or other materials provided with the distribution.
0026  *
0027  * 3. The name of the author may not be used to endorse or promote products
0028  * derived from this software without specific prior written permission.
0029  *
0030  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
0031  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0032  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
0033  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
0034  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
0035  * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0036  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0037  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0038  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
0039  * OF SUCH DAMAGE.
0040  *
0041  ******************************************************************************/
0042
0043 #include <stddef.h>
0044 #include <bsp/alt_address_space.h>
0045 #include <bsp/socal/alt_l3.h>
0046 #include <bsp/socal/socal.h>
0047 #include <bsp/socal/alt_acpidmap.h>
0048 #include <bsp/hwlib.h>
0049
0050
0051 #define ALT_ACP_ID_MAX_INPUT_ID     7
0052 #define ALT_ACP_ID_MAX_OUTPUT_ID    4096
0053
0054 /******************************************************************************/
0055 ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,
0056                                      ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,
0057                                      ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_bridge_attr,
0058                                      ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_bridge_attr)
0059 {
0060     uint32_t remap_reg_val = 0;
0061
0062     // Parameter checking and validation...
0063     if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM)
0064     {
0065         remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_BOOTROM);
0066     }
0067     else if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM)
0068     {
0069         remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_OCRAM);
0070     }
0071     else
0072     {
0073         return ALT_E_INV_OPTION;
0074     }
0075
0076     if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM)
0077     {
0078         remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_SDRAM);
0079     }
0080     else if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM)
0081     {
0082         remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_OCRAM);
0083     }
0084     else
0085     {
0086         return ALT_E_INV_OPTION;
0087     }
0088
0089     if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_INACCESSIBLE)
0090     {
0091         remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_INVISIBLE);
0092     }
0093     else if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_ACCESSIBLE)
0094     {
0095         remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_VISIBLE);
0096     }
0097     else
0098     {
0099         return ALT_E_INV_OPTION;
0100     }
0101
0102     if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_INACCESSIBLE)
0103     {
0104         remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_INVISIBLE);
0105     }
0106     else if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_ACCESSIBLE)
0107     {
0108         remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_VISIBLE);
0109     }
0110     else
0111     {
0112         return ALT_E_INV_OPTION;
0113     }
0114
0115     // Perform the remap.
0116     alt_write_word(ALT_L3_REMAP_ADDR, remap_reg_val);
0117
0118     return ALT_E_SUCCESS;
0119 }
0120
0121 /******************************************************************************/
0122 // Remap the MPU address space view of address 0 to access the SDRAM controller.
0123 // This is done by setting the L2 cache address filtering register start address
0124 // to 0 and leaving the address filtering address end address value
0125 // unmodified. This causes all physical addresses in the range
0126 // address_filter_start <= physical_address < address_filter_end to be directed
0127 // to the to the AXI Master Port M1 which is connected to the SDRAM
0128 // controller. All other addresses are directed to AXI Master Port M0 which
0129 // connect the MPU subsystem to the L3 interconnect.
0130 //
0131 // It is unnecessary to modify the MPU remap options in the L3 remap register
0132 // because those options only affect addresses in the MPU subsystem address
0133 // ranges that are now redirected to the SDRAM controller and never reach the L3
0134 // interconnect anyway.
0135 ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void)
0136 {
0137     uint32_t addr_filt_end = (alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR) &
0138                               L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
0139     return alt_l2_addr_filter_cfg_set(0x0, addr_filt_end);
0140 }
0141
0142 /******************************************************************************/
0143 // Return the L2 cache address filtering registers configuration settings in the
0144 // user provided start and end address range out parameters.
0145 ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
0146                                            uint32_t* addr_filt_end)
0147 {
0148     if (addr_filt_start == NULL || addr_filt_end == NULL)
0149     {
0150         return ALT_E_BAD_ARG;
0151     }
0152
0153     uint32_t addr_filt_start_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_START_ADDR);
0154     uint32_t addr_filt_end_reg   = alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR);
0155
0156     *addr_filt_start = (addr_filt_start_reg & L2_CACHE_ADDR_FILTERING_START_ADDR_MASK);
0157     *addr_filt_end = (addr_filt_end_reg & L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
0158     return ALT_E_SUCCESS;
0159 }
0160
0161 /******************************************************************************/
0162 ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,
0163                                            uint32_t addr_filt_end)
0164 {
0165     // Address filtering start and end values must be 1 MB aligned.
0166     if (  (addr_filt_start & ~L2_CACHE_ADDR_FILTERING_START_ADDR_MASK)
0167        || (addr_filt_end   & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK)  )
0168     {
0169         return ALT_E_ARG_RANGE;
0170     }
0171
0172     // While it is possible to set the address filtering end value above its
0173     // reset value and thereby access a larger SDRAM address range, it is not
0174     // recommended. Doing so would potentially obscure any mapped HPS to FPGA
0175     // bridge address spaces and peripherals on the L3 interconnect.
0176     if (addr_filt_end > L2_CACHE_ADDR_FILTERING_END_RESET)
0177     {
0178         return ALT_E_ARG_RANGE;
0179     }
0180
0181     // NOTE: ARM (ARM DDI 0246F CoreLink Level 2 Cache Controller L2C-310 TRM)
0182     // recommends programming the Address Filtering End Register before the
0183     // Address Filtering Start Register to avoid unpredictable behavior between
0184     // the two writes.
0185     alt_write_word(L2_CACHE_ADDR_FILTERING_END_ADDR, addr_filt_end);
0186     // It is recommended that address filtering always remain enabled.
0187     addr_filt_start |= L2_CACHE_ADDR_FILTERING_ENABLE_MASK;
0188     alt_write_word(L2_CACHE_ADDR_FILTERING_START_ADDR, addr_filt_start);
0189
0190     return ALT_E_SUCCESS;
0191 }
0192
0193 /******************************************************************************/
0194 ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id,
0195                                               const uint32_t output_id,
0196                                               const ALT_ACP_ID_MAP_PAGE_t page,
0197                                               const uint32_t aruser)
0198 {
0199     if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
0200     {
0201         return ALT_E_BAD_ARG;
0202     }
0203
0204     switch (output_id)
0205     {
0206     case ALT_ACP_ID_OUT_FIXED_ID_2:
0207         alt_write_word(ALT_ACPIDMAP_VID2RD_ADDR,
0208                          ALT_ACPIDMAP_VID2RD_MID_SET(input_id)
0209                        | ALT_ACPIDMAP_VID2RD_PAGE_SET(page)
0210                        | ALT_ACPIDMAP_VID2RD_USER_SET(aruser)
0211                        | ALT_ACPIDMAP_VID2RD_FORCE_SET(1UL));
0212         break;
0213     case ALT_ACP_ID_OUT_DYNAM_ID_3:
0214         alt_write_word(ALT_ACPIDMAP_VID3RD_ADDR,
0215                          ALT_ACPIDMAP_VID3RD_MID_SET(input_id)
0216                        | ALT_ACPIDMAP_VID3RD_PAGE_SET(page)
0217                        | ALT_ACPIDMAP_VID3RD_USER_SET(aruser)
0218                        | ALT_ACPIDMAP_VID3RD_FORCE_SET(1UL));
0219         break;
0220     case ALT_ACP_ID_OUT_DYNAM_ID_4:
0221         alt_write_word(ALT_ACPIDMAP_VID4RD_ADDR,
0222                          ALT_ACPIDMAP_VID4RD_MID_SET(input_id)
0223                        | ALT_ACPIDMAP_VID4RD_PAGE_SET(page)
0224                        | ALT_ACPIDMAP_VID4RD_USER_SET(aruser)
0225                        | ALT_ACPIDMAP_VID4RD_FORCE_SET(1UL));
0226         break;
0227     case ALT_ACP_ID_OUT_DYNAM_ID_5:
0228         alt_write_word(ALT_ACPIDMAP_VID5RD_ADDR,
0229                          ALT_ACPIDMAP_VID5RD_MID_SET(input_id)
0230                        | ALT_ACPIDMAP_VID5RD_PAGE_SET(page)
0231                        | ALT_ACPIDMAP_VID5RD_USER_SET(aruser)
0232                        | ALT_ACPIDMAP_VID5RD_FORCE_SET(1UL));
0233         break;
0234     case ALT_ACP_ID_OUT_DYNAM_ID_6:
0235         alt_write_word(ALT_ACPIDMAP_VID6RD_ADDR,
0236                          ALT_ACPIDMAP_VID6RD_MID_SET(input_id)
0237                        | ALT_ACPIDMAP_VID6RD_PAGE_SET(page)
0238                        | ALT_ACPIDMAP_VID6RD_USER_SET(aruser)
0239                        | ALT_ACPIDMAP_VID6RD_FORCE_SET(1UL));
0240         break;
0241     default:
0242         return ALT_E_BAD_ARG;
0243     }
0244
0245     return ALT_E_SUCCESS;
0246 }
0247
0248 /******************************************************************************/
0249 ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id,
0250                                                const uint32_t output_id,
0251                                                const ALT_ACP_ID_MAP_PAGE_t page,
0252                                                const uint32_t awuser)
0253 {
0254     if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
0255     {
0256         return ALT_E_BAD_ARG;
0257     }
0258
0259     switch (output_id)
0260     {
0261     case ALT_ACP_ID_OUT_FIXED_ID_2:
0262         alt_write_word(ALT_ACPIDMAP_VID2WR_ADDR,
0263                          ALT_ACPIDMAP_VID2WR_MID_SET(input_id)
0264                        | ALT_ACPIDMAP_VID2WR_PAGE_SET(page)
0265                        | ALT_ACPIDMAP_VID2WR_USER_SET(awuser)
0266                        | ALT_ACPIDMAP_VID2WR_FORCE_SET(1UL));
0267         break;
0268     case ALT_ACP_ID_OUT_DYNAM_ID_3:
0269         alt_write_word(ALT_ACPIDMAP_VID3WR_ADDR,
0270                          ALT_ACPIDMAP_VID3WR_MID_SET(input_id)
0271                        | ALT_ACPIDMAP_VID3WR_PAGE_SET(page)
0272                        | ALT_ACPIDMAP_VID3WR_USER_SET(awuser)
0273                        | ALT_ACPIDMAP_VID3WR_FORCE_SET(1UL));
0274         break;
0275     case ALT_ACP_ID_OUT_DYNAM_ID_4:
0276         alt_write_word(ALT_ACPIDMAP_VID4WR_ADDR,
0277                          ALT_ACPIDMAP_VID4WR_MID_SET(input_id)
0278                        | ALT_ACPIDMAP_VID4WR_PAGE_SET(page)
0279                        | ALT_ACPIDMAP_VID4WR_USER_SET(awuser)
0280                        | ALT_ACPIDMAP_VID4WR_FORCE_SET(1UL));
0281         break;
0282     case ALT_ACP_ID_OUT_DYNAM_ID_5:
0283         alt_write_word(ALT_ACPIDMAP_VID5WR_ADDR,
0284                          ALT_ACPIDMAP_VID5WR_MID_SET(input_id)
0285                        | ALT_ACPIDMAP_VID5WR_PAGE_SET(page)
0286                        | ALT_ACPIDMAP_VID5WR_USER_SET(awuser)
0287                        | ALT_ACPIDMAP_VID5WR_FORCE_SET(1UL));
0288         break;
0289     case ALT_ACP_ID_OUT_DYNAM_ID_6:
0290         alt_write_word(ALT_ACPIDMAP_VID6WR_ADDR,
0291                          ALT_ACPIDMAP_VID6WR_MID_SET(input_id)
0292                        | ALT_ACPIDMAP_VID6WR_PAGE_SET(page)
0293                        | ALT_ACPIDMAP_VID6WR_USER_SET(awuser)
0294                        | ALT_ACPIDMAP_VID6WR_FORCE_SET(1UL)
0295             );
0296         break;
0297     default:
0298         return ALT_E_BAD_ARG;
0299     }
0300
0301     return ALT_E_SUCCESS;
0302 }
0303
0304 /******************************************************************************/
0305 ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id)
0306 {
0307     if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
0308     {
0309         return ALT_E_BAD_ARG;
0310     }
0311
0312     uint32_t aruser, page;
0313
0314     switch (output_id)
0315     {
0316     case ALT_ACP_ID_OUT_FIXED_ID_2:
0317         aruser = ALT_ACPIDMAP_VID2RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));
0318         page = ALT_ACPIDMAP_VID2RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));
0319         break;
0320     case ALT_ACP_ID_OUT_DYNAM_ID_3:
0321         aruser = ALT_ACPIDMAP_VID3RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));
0322         page = ALT_ACPIDMAP_VID3RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));
0323         break;
0324     case ALT_ACP_ID_OUT_DYNAM_ID_4:
0325         aruser = ALT_ACPIDMAP_VID4RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));
0326         page = ALT_ACPIDMAP_VID4RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));
0327         break;
0328     case ALT_ACP_ID_OUT_DYNAM_ID_5:
0329         aruser = ALT_ACPIDMAP_VID5RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));
0330         page = ALT_ACPIDMAP_VID5RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));
0331         break;
0332     case ALT_ACP_ID_OUT_DYNAM_ID_6:
0333         aruser = ALT_ACPIDMAP_VID6RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));
0334         page = ALT_ACPIDMAP_VID6RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));
0335         break;
0336     default:
0337         return ALT_E_BAD_ARG;
0338     }
0339
0340     alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,
0341                      ALT_ACPIDMAP_DYNRD_PAGE_SET(page)
0342                    | ALT_ACPIDMAP_DYNRD_USER_SET(aruser));
0343     return ALT_E_SUCCESS;
0344 }
0345
0346 /******************************************************************************/
0347 ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id)
0348 {
0349     if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
0350     {
0351         return ALT_E_BAD_ARG;
0352     }
0353
0354     uint32_t awuser, page;
0355
0356     switch (output_id)
0357     {
0358     case ALT_ACP_ID_OUT_FIXED_ID_2:
0359         awuser = ALT_ACPIDMAP_VID2WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
0360         page   = ALT_ACPIDMAP_VID2WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
0361         break;
0362     case ALT_ACP_ID_OUT_DYNAM_ID_3:
0363         awuser = ALT_ACPIDMAP_VID3WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
0364         page   = ALT_ACPIDMAP_VID3WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
0365         break;
0366     case ALT_ACP_ID_OUT_DYNAM_ID_4:
0367         awuser = ALT_ACPIDMAP_VID4WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
0368         page   = ALT_ACPIDMAP_VID4WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
0369         break;
0370     case ALT_ACP_ID_OUT_DYNAM_ID_5:
0371         awuser = ALT_ACPIDMAP_VID5WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
0372         page   = ALT_ACPIDMAP_VID5WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
0373         break;
0374     case ALT_ACP_ID_OUT_DYNAM_ID_6:
0375         awuser = ALT_ACPIDMAP_VID6WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
0376         page   = ALT_ACPIDMAP_VID6WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
0377         break;
0378     default:
0379         return ALT_E_BAD_ARG;
0380     }
0381
0382     alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
0383                      ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
0384                    | ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
0385     return ALT_E_SUCCESS;
0386 }
0387
0388 /******************************************************************************/
0389 ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
0390                                                         const uint32_t aruser)
0391 {
0392     alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,
0393                      ALT_ACPIDMAP_DYNRD_PAGE_SET(page)
0394                    | ALT_ACPIDMAP_DYNRD_USER_SET(aruser));
0395     return ALT_E_SUCCESS;
0396 }
0397
0398 /******************************************************************************/
0399 ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
0400                                                          const uint32_t awuser)
0401 {
0402     alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
0403                      ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
0404                    | ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
0405     return ALT_E_SUCCESS;
0406 }
0407
0408 /******************************************************************************/
0409 ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id,
0410                                                 bool * fixed,
0411                                                 uint32_t * input_id,
0412                                                 ALT_ACP_ID_MAP_PAGE_t * page,
0413                                                 uint32_t * aruser)
0414 {
0415     if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
0416     {
0417         return ALT_E_BAD_ARG;
0418     }
0419
0420     switch (output_id)
0421     {
0422     case ALT_ACP_ID_OUT_FIXED_ID_2:
0423         *aruser   = ALT_ACPIDMAP_VID2RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
0424         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
0425         *input_id = ALT_ACPIDMAP_VID2RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
0426         *fixed    = ALT_ACPIDMAP_VID2RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
0427         break;
0428     case ALT_ACP_ID_OUT_DYNAM_ID_3:
0429         *aruser   = ALT_ACPIDMAP_VID3RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
0430         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
0431         *input_id = ALT_ACPIDMAP_VID3RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
0432         *fixed    = ALT_ACPIDMAP_VID3RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
0433         break;
0434     case ALT_ACP_ID_OUT_DYNAM_ID_4:
0435         *aruser   = ALT_ACPIDMAP_VID4RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
0436         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
0437         *input_id = ALT_ACPIDMAP_VID4RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
0438         *fixed    = ALT_ACPIDMAP_VID4RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
0439         break;
0440     case ALT_ACP_ID_OUT_DYNAM_ID_5:
0441         *aruser   = ALT_ACPIDMAP_VID5RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
0442         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
0443         *input_id = ALT_ACPIDMAP_VID5RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
0444         *fixed    = ALT_ACPIDMAP_VID5RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
0445         break;
0446     case ALT_ACP_ID_OUT_DYNAM_ID_6:
0447         *aruser   = ALT_ACPIDMAP_VID6RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
0448         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
0449         *input_id = ALT_ACPIDMAP_VID6RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
0450         *fixed    = ALT_ACPIDMAP_VID6RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
0451         break;
0452     case ALT_ACP_ID_OUT_DYNAM_ID_7:
0453         *aruser   = ALT_ACPIDMAP_DYNRD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));
0454         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNRD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));
0455         break;
0456     default:
0457         return ALT_E_BAD_ARG;
0458     }
0459
0460     return ALT_E_SUCCESS;
0461 }
0462
0463 ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id,
0464                                                  bool * fixed,
0465                                                  uint32_t * input_id,
0466                                                  ALT_ACP_ID_MAP_PAGE_t * page,
0467                                                  uint32_t * awuser)
0468 {
0469     if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
0470     {
0471         return ALT_E_BAD_ARG;
0472     }
0473
0474     switch (output_id)
0475     {
0476     case ALT_ACP_ID_OUT_FIXED_ID_2:
0477         *awuser   = ALT_ACPIDMAP_VID2WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
0478         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
0479         *input_id = ALT_ACPIDMAP_VID2WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
0480         *fixed    = ALT_ACPIDMAP_VID2WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
0481         break;
0482     case ALT_ACP_ID_OUT_DYNAM_ID_3:
0483         *awuser   = ALT_ACPIDMAP_VID3WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
0484         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
0485         *input_id = ALT_ACPIDMAP_VID3WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
0486         *fixed    = ALT_ACPIDMAP_VID3WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
0487         break;
0488     case ALT_ACP_ID_OUT_DYNAM_ID_4:
0489         *awuser   = ALT_ACPIDMAP_VID4WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
0490         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
0491         *input_id = ALT_ACPIDMAP_VID4WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
0492         *fixed    = ALT_ACPIDMAP_VID4WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
0493         break;
0494     case ALT_ACP_ID_OUT_DYNAM_ID_5:
0495         *awuser   = ALT_ACPIDMAP_VID5WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
0496         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
0497         *input_id = ALT_ACPIDMAP_VID5WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
0498         *fixed    = ALT_ACPIDMAP_VID5WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
0499         break;
0500     case ALT_ACP_ID_OUT_DYNAM_ID_6:
0501         *awuser   = ALT_ACPIDMAP_VID6WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
0502         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
0503         *input_id = ALT_ACPIDMAP_VID6WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
0504         *fixed    = ALT_ACPIDMAP_VID6WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
0505         break;
0506     case ALT_ACP_ID_OUT_DYNAM_ID_7:
0507         *awuser   = ALT_ACPIDMAP_DYNWR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
0508         *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNWR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
0509         break;
0510     default:
0511         return ALT_E_BAD_ARG;
0512     }
0513
0514     return ALT_E_SUCCESS;
0515 }