include/bsp/ecc.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsAArch64XilinxZynqMP
0007  *
0008  * @brief This header file provides internal APIs for managing ECC events.
0009  */
0010
0011 /*
0012  * Copyright (C) 2024 On-Line Applications Research Corporation (OAR)
0013  * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifndef LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_ECC_H
0038 #define LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_ECC_H
0039
0040 /**
0041  * @addtogroup RTEMSBSPsAArch64
0042  *
0043  * @{
0044  */
0045
0046 //#include <bspopts.h>
0047
0048 #ifndef ASM
0049
0050 #ifdef __cplusplus
0051 extern "C" {
0052 #endif /* __cplusplus */
0053
0054 /**
0055  * @brief Enumeration describing the possible types of ECC events
0056  */
0057 typedef enum {
0058   /* L1 Cache event information is delivered via Cache_Error_Info struct. */
0059   L1_CACHE,
0060   /* L2 Cache event information is delivered via Cache_Error_Info struct. */
0061   L2_CACHE,
0062   /*
0063    * L1 and L2 cache are on a combined interrupt on ZynqMP. They are enabled as
0064    * a single unit. The above individual L1 and L2 cache definitions will be
0065    * used for reporting. Attempting to enable L1 or L2 individually will enable
0066    * both.
0067    */
0068   L1_L2_CACHE,
0069   /* OCM RAM event information is delivered via OCM_Error_Info struct. */
0070   OCM_RAM,
0071   /* DDR RAM event information is delivered via DDR_Error_Info struct. */
0072   DDR_RAM,
0073 } ECC_Event_Type;
0074
0075 /**
0076  * @brief The specific locations where a cache error can originate
0077  */
0078 typedef enum {
0079   RAM_ID_L1I_TAG,
0080   RAM_ID_L1I_DATA,
0081   RAM_ID_L1D_TAG,
0082   RAM_ID_L1D_DATA,
0083   RAM_ID_L1D_DIRTY,
0084   RAM_ID_TLB,
0085   RAM_ID_L2_TAG,
0086   RAM_ID_L2_DATA,
0087   RAM_ID_SCU,
0088   RAM_ID_UNKNOWN
0089 } Cache_Error_RAM_ID;
0090
0091 /**
0092  * @brief Structure containing information about a Cache error
0093  */
0094 typedef struct {
0095   /* Indicates the RAM index address */
0096   uint64_t address;
0097   /* Indicates the type of RAM where the error originated */
0098   Cache_Error_RAM_ID ramid;
0099   /*
0100    * Indicates the segment (way or bank) of the RAM where the error originated.
0101    * Does not apply to L1D_DIRTY RAM ID. For SCU errors, this also indicates the
0102    * associated CPU.
0103    */
0104   uint8_t segment;
0105   /* The number of times this specific error has occurred since last reset */
0106   uint8_t repeats;
0107   /* The number of times other errors have occurred since last reset */
0108   uint8_t other_errors;
0109   /* Whether any of the errors represented have caused a data abort */
0110   bool abort;
0111 } Cache_Error_Info;
0112
0113 /**
0114  * @brief Typedef for ECC handlers
0115  *
0116  * Functions matching this prototype can be registered as the handler for ECC
0117  * event callbacks. The data argument is a struct describing the event that
0118  * occurred.
0119  */
0120 typedef void (*zynqmp_ecc_handler)( ECC_Event_Type event, void *data );
0121
0122 /**
0123  * @brief Enumeration describing the possible types of ECC events
0124  *
0125  * Note that the provided handler may be called from interrupt context.
0126  *
0127  * @param handler The handler to be called for all ECC error events
0128  */
0129 void zynqmp_ecc_register_handler( zynqmp_ecc_handler handler );
0130
0131 /**
0132  * @brief Enable ECC error reporting
0133  *
0134  * Enables ECC error reporting for the specified subsystem.
0135  *
0136  * @param event The ECC error event type to enable
0137  */
0138 int zynqmp_ecc_enable( ECC_Event_Type event );
0139
0140 /**
0141  * @brief Injects an ECC fault in the On-Chip Memory (OCM)
0142  */
0143 void zynqmp_ocm_inject_fault( void );
0144
0145 /**
0146  * @brief The types of OCM ECC errors
0147  */
0148 typedef enum {
0149   OCM_UNCORRECTABLE,
0150   OCM_UNCORRECTABLE_RMW,
0151   OCM_CORRECTABLE
0152 } OCM_Error_Type;
0153
0154 /**
0155  * @brief Structure containing information about a OCM ECC error
0156  */
0157 typedef struct {
0158   /* Describes the type of error being reported */
0159   OCM_Error_Type type;
0160   /* The offset into OCM where the error occurred */
0161   uint32_t offset;
0162   /* The data relevant to the error. Does not apply to RMW errors */
0163   uint32_t data0;
0164   uint32_t data1;
0165   uint32_t data2;
0166   uint32_t data3;
0167   /* The ECC syndrome relevant to the error. Does not apply to RMW errors */
0168   uint16_t syndrome;
0169 } OCM_Error_Info;
0170
0171 /**
0172  * @brief The types of DDR ECC errors
0173  */
0174 typedef enum {
0175   DDR_UNCORRECTABLE,
0176   DDR_CORRECTABLE
0177 } DDR_Error_Type;
0178
0179 /**
0180  * @brief Structure containing information about a DDR ECC error
0181  */
0182 typedef struct {
0183   /* Describes the type of error being reported */
0184   DDR_Error_Type type;
0185   /* The DDR Rank where the error occurred */
0186   uint32_t rank;
0187   /* The DDR Bank Group where the error occurred */
0188   uint32_t bank_group;
0189   /* The DDR Bank where the error occurred */
0190   uint32_t bank;
0191   /* The DDR Row where the error occurred */
0192   uint32_t row;
0193   /* The DDR Column where the error occurred */
0194   uint32_t column;
0195   /*
0196    * When mapping from SDRAM addressing back to AXI addressing, this is will
0197    * only be a close approximation of the source address since bits can be
0198    * discarded when converting from AXI to SDRAM.
0199    */
0200   uint64_t address;
0201 } DDR_Error_Info;
0202
0203 #ifdef __cplusplus
0204 }
0205 #endif /* __cplusplus */
0206
0207 #endif /* ASM */
0208
0209 /** @} */
0210
0211 #endif /* LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_ECC_H */