xilinx-zynqmp/ecc/cache.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsAArch64XilinxZynqMP
0007  *
0008  * @brief This source file contains the implementation of zynqmp_ecc_init().
0009  */
0010
0011 /*
0012  * Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
0013  * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #include <bsp.h>
0038 #include <bsp/ecc_priv.h>
0039 #include <bsp/irq.h>
0040 #include <bsp/utility.h>
0041 #include <rtems/score/aarch64-system-registers.h>
0042
0043 static Cache_Error_RAM_ID get_l1_ramid(uint64_t ramid)
0044 {
0045   switch (ramid) {
0046   case 0x0:
0047     return RAM_ID_L1I_TAG;
0048   case 0x1:
0049     return RAM_ID_L1I_DATA;
0050   case 0x8:
0051     return RAM_ID_L1D_TAG;
0052   case 0x9:
0053     return RAM_ID_L1D_DATA;
0054   case 0xa:
0055     return RAM_ID_L1D_DIRTY;
0056   case 0x18:
0057     return RAM_ID_TLB;
0058   default:
0059     return RAM_ID_UNKNOWN;
0060   }
0061 }
0062
0063 static Cache_Error_RAM_ID get_l2_ramid(uint64_t ramid)
0064 {
0065   switch (ramid) {
0066   case 0x10:
0067     return RAM_ID_L2_TAG;
0068   case 0x11:
0069     return RAM_ID_L2_DATA;
0070   case 0x12:
0071     return RAM_ID_SCU;
0072   default:
0073     return RAM_ID_UNKNOWN;
0074   }
0075 }
0076
0077 static void cache_handler(void *arg)
0078 {
0079   uint64_t l1val = _AArch64_Read_cpumerrsr_el1();
0080   _AArch64_Write_cpumerrsr_el1(l1val);
0081   uint64_t l2val = _AArch64_Read_l2merrsr_el1();
0082   _AArch64_Write_l2merrsr_el1(l2val);
0083
0084   (void) arg;
0085
0086   if (l1val & AARCH64_CPUMERRSR_EL1_VALID) {
0087     /* parse L1 data */
0088     Cache_Error_Info cerr = {0, };
0089     cerr.abort = l1val & AARCH64_CPUMERRSR_EL1_FATAL;
0090     cerr.repeats = AARCH64_CPUMERRSR_EL1_REPEATERR_GET(l1val);
0091     cerr.other_errors = AARCH64_CPUMERRSR_EL1_OTHERERR_GET(l1val);
0092     cerr.ramid = get_l1_ramid(AARCH64_CPUMERRSR_EL1_RAMID_GET(l1val));
0093     cerr.segment = AARCH64_CPUMERRSR_EL1_CPUIDWAY_GET(l1val);
0094     cerr.address = AARCH64_CPUMERRSR_EL1_ADDR_GET(l1val);
0095
0096     zynqmp_invoke_ecc_handler(L1_CACHE, &cerr);
0097   }
0098
0099   if (l2val & AARCH64_L2MERRSR_EL1_VALID) {
0100     /* parse L2 data */
0101     Cache_Error_Info cerr = {0, };
0102     cerr.abort = l2val & AARCH64_L2MERRSR_EL1_FATAL;
0103     cerr.repeats = AARCH64_L2MERRSR_EL1_REPEATERR_GET(l2val);
0104     cerr.other_errors = AARCH64_L2MERRSR_EL1_OTHERERR_GET(l2val);
0105     cerr.ramid = get_l2_ramid(AARCH64_L2MERRSR_EL1_RAMID_GET(l2val));
0106     cerr.segment = AARCH64_L2MERRSR_EL1_CPUIDWAY_GET(l2val);
0107     cerr.address = AARCH64_L2MERRSR_EL1_ADDR_GET(l2val);
0108
0109     zynqmp_invoke_ecc_handler(L2_CACHE, &cerr);
0110   }
0111 }
0112
0113 static rtems_interrupt_entry zynqmp_cache_ecc_entry;
0114
0115 rtems_status_code zynqmp_configure_cache_ecc( void )
0116 {
0117   rtems_interrupt_entry_initialize(
0118     &zynqmp_cache_ecc_entry,
0119     cache_handler,
0120     NULL,
0121     "L1/L2 Cache Errors"
0122   );
0123
0124   return rtems_interrupt_entry_install(
0125     ZYNQMP_IRQ_CACHE,
0126     RTEMS_INTERRUPT_SHARED,
0127     &zynqmp_cache_ecc_entry
0128   );
0129 }