shared/start/aarch64-smp.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsAArch64Shared
0007  *
0008  * @brief SMP startup and interop code.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
0013  * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #include <rtems/score/smpimpl.h>
0038
0039 #include <bsp/irq.h>
0040
0041 static void bsp_inter_processor_interrupt( void *arg )
0042 {
0043   _SMP_Inter_processor_interrupt_handler( _Per_CPU_Get() );
0044 }
0045
0046 uint32_t _CPU_SMP_Initialize( void )
0047 {
0048   return arm_gic_irq_processor_count();
0049 }
0050
0051 static rtems_interrupt_entry aarch64_ipi_entry;
0052
0053 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
0054 {
0055   rtems_status_code sc;
0056
0057   rtems_interrupt_entry_initialize(
0058     &aarch64_ipi_entry,
0059     bsp_inter_processor_interrupt,
0060     NULL,
0061     "IPI"
0062   );
0063   sc = rtems_interrupt_entry_install(
0064     ARM_GIC_IRQ_SGI_0,
0065     RTEMS_INTERRUPT_UNIQUE,
0066     &aarch64_ipi_entry
0067   );
0068   _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
0069 }
0070
0071 void _CPU_SMP_Prepare_start_multitasking( void )
0072 {
0073   /* Do nothing */
0074 }
0075
0076 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
0077 {
0078   arm_gic_trigger_sgi(
0079     ARM_GIC_IRQ_SGI_0,
0080     1U << target_processor_index
0081   );
0082 }
0083
0084 uint32_t _CPU_SMP_Get_current_processor( void )
0085 {
0086   return _Per_CPU_Get_index( _CPU_Get_current_per_CPU_control() );
0087 }