shared/mmu/vmsav8-64.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsAArch64Shared
0007  *
0008  * @brief AArch64 MMU implementation.
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
0013  * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #include <bsp/aarch64-mmu.h>
0038 #include <rtems/score/cpu.h>
0039
0040 /*
0041  * This must have a non-header implementation because it is used by libdebugger.
0042  */
0043 rtems_status_code aarch64_mmu_map(
0044   uintptr_t addr,
0045   uint64_t size,
0046   uint64_t flags
0047 )
0048 {
0049   aarch64_mmu_config_entry config = {
0050     .begin = addr,
0051     .end = addr + size,
0052     .flags = flags
0053   };
0054   rtems_status_code sc;
0055   ISR_Level        level;
0056   aarch64_mmu_control *control = &aarch64_mmu_instance;
0057
0058   /*
0059    * Disable interrupts so they don't run while the MMU tables are being
0060    * modified.
0061    */
0062   _ISR_Local_disable( level );
0063
0064   sc = aarch64_mmu_set_translation_table_entries(
0065     control,
0066     &config
0067   );
0068   _AARCH64_Data_synchronization_barrier();
0069   __asm__ volatile(
0070     "tlbi vmalle1\n"
0071   );
0072   _AARCH64_Data_synchronization_barrier();
0073   _AARCH64_Instruction_synchronization_barrier();
0074
0075   _ISR_Local_enable( level );
0076
0077   return sc;
0078 }