shared/clock/arm-generic-timer-aarch64.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsAArch64Shared
0007  *
0008  * @brief AArch64-specific ARM GPT system register accessors.
0009  */
0010
0011 /*
0012  * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
0013  * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #include <dev/clock/arm-generic-timer.h>
0038 #include <bsp/irq.h>
0039
0040 uint64_t arm_gt_clock_get_compare_value(void)
0041 {
0042   uint64_t val;
0043   __asm__ volatile (
0044 #ifdef AARCH64_GENERIC_TIMER_USE_VIRTUAL
0045     "mrs %[val], cntv_cval_el0"
0046 #elif defined(AARCH64_GENERIC_TIMER_USE_PHYSICAL_SECURE)
0047     "mrs %[val], cntps_cval_el1"
0048 #else
0049     "mrs %[val], cntp_cval_el0"
0050 #endif
0051     : [val] "=&r" (val)
0052   );
0053   return val;
0054 }
0055
0056 void arm_gt_clock_set_compare_value(uint64_t cval)
0057 {
0058   __asm__ volatile (
0059 #ifdef AARCH64_GENERIC_TIMER_USE_VIRTUAL
0060     "msr cntv_cval_el0, %[cval]"
0061 #elif defined(AARCH64_GENERIC_TIMER_USE_PHYSICAL_SECURE)
0062     "msr cntps_cval_el1, %[cval]"
0063 #else
0064     "msr cntp_cval_el0, %[cval]"
0065 #endif
0066     :
0067     : [cval] "r" (cval)
0068   );
0069 }
0070
0071 uint64_t arm_gt_clock_get_count(void)
0072 {
0073   uint64_t val;
0074   __asm__ volatile (
0075 #ifdef AARCH64_GENERIC_TIMER_USE_VIRTUAL
0076     "mrs %[val], cntvct_el0"
0077 #else
0078     "mrs %[val], cntpct_el0"
0079 #endif
0080     : [val] "=&r" (val)
0081   );
0082   return val;
0083 }
0084
0085 void arm_gt_clock_set_control(uint32_t ctl)
0086 {
0087   __asm__ volatile (
0088 #ifdef AARCH64_GENERIC_TIMER_USE_VIRTUAL
0089     "msr cntv_ctl_el0, %[ctl]"
0090 #elif defined(AARCH64_GENERIC_TIMER_USE_PHYSICAL_SECURE)
0091     "msr cntps_ctl_el1, %[ctl]"
0092 #else
0093     "msr cntp_ctl_el0, %[ctl]"
0094 #endif
0095     :
0096     : [ctl] "r" (ctl)
0097   );
0098 }
0099
0100 void arm_generic_timer_get_config( uint32_t *frequency, uint32_t *irq )
0101 {
0102   uint64_t val;
0103   __asm__ volatile (
0104     "mrs %[val], cntfrq_el0"
0105     : [val] "=&r" (val)
0106   );
0107   *frequency = val;
0108
0109 #ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
0110   *irq = BSP_TIMER_VIRT_PPI;
0111 #elif defined(AARCH64_GENERIC_TIMER_USE_PHYSICAL_SECURE)
0112   *irq = BSP_TIMER_PHYS_S_PPI;
0113 #else
0114   *irq = BSP_TIMER_PHYS_NS_PPI;
0115 #endif
0116 }