include/bsp/raspberrypi.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup raspberrypi_4_regs
0005  *
0006  * @brief Register definitions.
0007  */
0008
0009 /*
0010  *  Copyright (c) 2022 Mohd Noor Aman
0011  *  Copyright (c) 2024 Ning Yang
0012  *
0013  *  The license and distribution terms for this file may be
0014  *  found in the file LICENSE in this distribution or at
0015  *
0016  *  http://www.rtems.org/license/LICENSE
0017  *
0018  */
0019
0020
0021 #ifndef LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
0022 #define LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
0023
0024
0025 #include <bspopts.h>
0026 #include <stdint.h>
0027 #include <bsp/utility.h>
0028
0029
0030 /**
0031  * @defgroup raspberrypi_reg Register Definitions
0032  *
0033  * @ingroup RTEMSBSPsARMRaspberryPi
0034  *
0035  * @brief Register Definitions
0036  *
0037  * @{
0038  */
0039
0040 /**
0041  * @name Register Macros
0042  *
0043  * @{
0044  */
0045
0046 #define BCM2711_REG(x)           (*(volatile uint64_t *)(x))
0047 #define BCM2711_BIT(n)           (1 << (n))
0048 #define BCM2835_REG(addr)        (*(volatile uint32_t*)(addr))
0049
0050 /** @} */
0051
0052 /**
0053  * @name Peripheral Base Register Address
0054  *
0055  * @{
0056  */
0057
0058 #define RPI_PERIPHERAL_BASE         0xFE000000
0059 #define BASE_OFFSET                 0xFE000000
0060 #define RPI_PERIPHERAL_SIZE         0x01800000
0061
0062 /**
0063  * @name Bus to Physical address translation
0064  *       Macro.
0065  * @{
0066  */
0067 #define BUS_TO_PHY(x)            ((x) - BASE_OFFSET)
0068
0069 /** @} */
0070
0071 /**
0072  * @name Internal ARM Timer Registers
0073  *
0074  * @{
0075  */
0076
0077 #define BCM2711_CLOCK_FREQ       250000000
0078
0079 #define BCM2711_TIMER_BASE       (RPI_PERIPHERAL_BASE + 0xB400)
0080
0081 #define BCM2711_TIMER_LOD        (BCM2711_TIMER_BASE + 0x00)
0082 #define BCM2711_TIMER_VAL        (BCM2711_TIMER_BASE + 0x04)
0083 #define BCM2711_TIMER_CTL        (BCM2711_TIMER_BASE + 0x08)
0084 #define BCM2711_TIMER_CLI        (BCM2711_TIMER_BASE + 0x0C)
0085 #define BCM2711_TIMER_RIS        (BCM2711_TIMER_BASE + 0x10)
0086 #define BCM2711_TIMER_MIS        (BCM2711_TIMER_BASE + 0x14)
0087 #define BCM2711_TIMER_RLD        (BCM2711_TIMER_BASE + 0x18)
0088 #define BCM2711_TIMER_DIV        (BCM2711_TIMER_BASE + 0x1C)
0089 #define BCM2711_TIMER_CNT        (BCM2711_TIMER_BASE + 0x20)
0090
0091 #define BCM2711_TIMER_PRESCALE    0xF9
0092
0093 /** @} */
0094
0095 /**
0096  * @name Power Management and Watchdog Registers
0097  *
0098  * @{
0099  */
0100
0101 #define BCM2711_PM_PASSWD_MAGIC  0x5a000000
0102
0103 #define BCM2711_PM_BASE          (RPI_PERIPHERAL_BASE + 0x100000)
0104
0105 #define BCM2711_PM_GNRIC         (BCM2711_PM_BASE + 0x00)
0106 #define BCM2711_PM_GNRIC_POWUP   0x00000001
0107 #define BCM2711_PM_GNRIC_POWOK   0x00000002
0108 #define BCM2711_PM_GNRIC_ISPOW   0x00000004
0109 #define BCM2711_PM_GNRIC_MEMREP  0x00000008
0110 #define BCM2711_PM_GNRIC_MRDONE  0x00000010
0111 #define BCM2711_PM_GNRIC_ISFUNC  0x00000020
0112 #define BCM2711_PM_GNRIC_RSTN    0x00000fc0
0113 #define BCM2711_PM_GNRIC_ENAB    0x00001000
0114 #define BCM2711_PM_GNRIC_CFG     0x007f0000
0115
0116 #define BCM2711_PM_AUDIO         (BCM2711_PM_BASE + 0x04)
0117 #define BCM2711_PM_AUDIO_APSM    0x000fffff
0118 #define BCM2711_PM_AUDIO_CTRLEN  0x00100000
0119 #define BCM2711_PM_AUDIO_RSTN    0x00200000
0120
0121 #define BCM2711_PM_STATUS        (BCM2711_PM_BASE + 0x18)
0122
0123 #define BCM2711_PM_RSTC          (BCM2711_PM_BASE + 0x1c)
0124 #define BCM2711_PM_RSTC_DRCFG    0x00000003
0125 #define BCM2711_PM_RSTC_WRCFG    0x00000030
0126 #define BCM2711_PM_RSTC_WRCFG_FULL   0x00000020
0127 #define BCM2711_PM_RSTC_WRCFG_CLR    0xffffffcf
0128 #define BCM2711_PM_RSTC_SRCFG    0x00000300
0129 #define BCM2711_PM_RSTC_QRCFG    0x00003000
0130 #define BCM2711_PM_RSTC_FRCFG    0x00030000
0131 #define BCM2711_PM_RSTC_HRCFG    0x00300000
0132 #define BCM2711_PM_RSTC_RESET    0x00000102
0133
0134 #define BCM2711_PM_RSTS          (BCM2711_PM_BASE + 0x20)
0135 #define BCM2711_PM_RSTS_HADDRQ   0x00000001
0136 #define BCM2711_PM_RSTS_HADDRF   0x00000002
0137 #define BCM2711_PM_RSTS_HADDRH   0x00000004
0138 #define BCM2711_PM_RSTS_HADWRQ   0x00000010
0139 #define BCM2711_PM_RSTS_HADWRF   0x0000002
0140 #define BCM2711_PM_RSTS_HADWRH   0x00000040
0141 #define BCM2711_PM_RSTS_HADSRQ   0x00000100
0142 #define BCM2711_PM_RSTS_HADSRF   0x00000200
0143 #define BCM2711_PM_RSTS_HADSRH   0x00000400
0144 #define BCM2711_PM_RSTS_HADPOR   0x00001000
0145
0146 #define BCM2711_PM_WDOG          (BCM2711_PM_BASE + 0x24)
0147 #define BCM2711_PM_WDOG_MASK     0x000fffff
0148
0149 /** @} */
0150
0151
0152 /** @} */
0153
0154 /**
0155  * @name AUX Registers
0156  *
0157  * @{
0158  */
0159
0160 #define BCM2711_AUX_BASE         (RPI_PERIPHERAL_BASE + 0x215000)
0161
0162 #define AUX_ENABLES              (BCM2711_AUX_BASE + 0x04)
0163 #define AUX_MU_IO_REG            (BCM2711_AUX_BASE + 0x40)
0164 #define AUX_MU_IER_REG           (BCM2711_AUX_BASE + 0x44)
0165 #define AUX_MU_IIR_REG           (BCM2711_AUX_BASE + 0x48)
0166 #define AUX_MU_LCR_REG           (BCM2711_AUX_BASE + 0x4C)
0167 #define AUX_MU_MCR_REG           (BCM2711_AUX_BASE + 0x50)
0168 #define AUX_MU_LSR_REG           (BCM2711_AUX_BASE + 0x54)
0169 #define AUX_MU_MSR_REG           (BCM2711_AUX_BASE + 0x58)
0170 #define AUX_MU_SCRATCH           (BCM2711_AUX_BASE + 0x5C)
0171 #define AUX_MU_CNTL_REG          (BCM2711_AUX_BASE + 0x60)
0172 #define AUX_MU_STAT_REG          (BCM2711_AUX_BASE + 0x64)
0173 #define AUX_MU_BAUD_REG          (BCM2711_AUX_BASE + 0x68)
0174
0175 /** @} */
0176
0177 /**
0178  * @name PL011 UARTs
0179  *
0180  * @{
0181  */
0182 #define BCM2711_PL011_BASE        (RPI_PERIPHERAL_BASE + 0x201000)
0183 #define BCM2711_PL011_SIZE        0xc00
0184 #define BCM2711_PL011_DEVICE_SIZE 0x200
0185
0186 #define BCM2711_UART0_BASE (BCM2711_PL011_BASE + 0x000)
0187 #define BCM2711_UART0_SIZE BCM2711_PL011_DEVICE_SIZE
0188 #define BCM2711_UART2_BASE (BCM2711_PL011_BASE + 0x400)
0189 #define BCM2711_UART2_SIZE BCM2711_PL011_DEVICE_SIZE
0190 #define BCM2711_UART3_BASE (BCM2711_PL011_BASE + 0x600)
0191 #define BCM2711_UART3_SIZE BCM2711_PL011_DEVICE_SIZE
0192 #define BCM2711_UART4_BASE (BCM2711_PL011_BASE + 0x800)
0193 #define BCM2711_UART4_SIZE BCM2711_PL011_DEVICE_SIZE
0194 #define BCM2711_UART5_BASE (BCM2711_PL011_BASE + 0xa00)
0195 #define BCM2711_UART5_SIZE BCM2711_PL011_DEVICE_SIZE
0196 /** @} */
0197
0198 /**
0199  * @name GPU Timer Registers
0200  *
0201  * @{
0202  */
0203
0204 /**
0205  * NOTE: The GPU uses Compare registers 0 and 2 for
0206  *       it's own RTOS. 1 and 3 are available for use in
0207  *       RTEMS.
0208  */
0209 #define BCM2711_GPU_TIMER_BASE       (RPI_PERIPHERAL_BASE + 0x3000)
0210
0211 #define BCM2711_GPU_TIMER_CS         (BCM2711_GPU_TIMER_BASE + 0x00)
0212 #define BCM2711_GPU_TIMER_CS_M0      0x00000001
0213 #define BCM2711_GPU_TIMER_CS_M1      0x00000002
0214 #define BCM2711_GPU_TIMER_CS_M2      0x00000004
0215 #define BCM2711_GPU_TIMER_CS_M3      0x00000008
0216 #define BCM2711_GPU_TIMER_CLO        (BCM2711_GPU_TIMER_BASE + 0x04)
0217 #define BCM2711_GPU_TIMER_CHI        (BCM2711_GPU_TIMER_BASE + 0x08)
0218 #define BCM2711_GPU_TIMER_C0         (BCM2711_GPU_TIMER_BASE + 0x0C)
0219 #define BCM2711_GPU_TIMER_C1         (BCM2711_GPU_TIMER_BASE + 0x10)
0220 #define BCM2711_GPU_TIMER_C2         (BCM2711_GPU_TIMER_BASE + 0x14)
0221 #define BCM2711_GPU_TIMER_C3         (BCM2711_GPU_TIMER_BASE + 0x18)
0222
0223 /**
0224  * NOTE: compatible with the BCM2835 system timer
0225  */
0226 #define BCM2835_GPU_TIMER_CS_M3      BCM2711_GPU_TIMER_CS_M3
0227 #define BCM2835_GPU_TIMER_C3         BCM2711_GPU_TIMER_C3
0228 #define BCM2835_GPU_TIMER_CLO        BCM2711_GPU_TIMER_CLO
0229 #define BCM2835_GPU_TIMER_CS         BCM2711_GPU_TIMER_CS
0230 /** @} */
0231
0232 /**
0233  * @name GPIO Registers
0234  *
0235  * @{
0236  */
0237
0238 #define BCM2711_GPIO_BASE (RPI_PERIPHERAL_BASE + 0x200000)
0239 #define BCM2711_GPIO_SIZE 0xf4
0240
0241 #define BCM2711_GPIO_PIN_COUNT 58
0242
0243 /** @} */
0244
0245 /**
0246  * @name EMMC Registers
0247  *
0248  * @{
0249  */
0250
0251 /**
0252  * NOTE: Since the SD controller follows the SDHCI standard,
0253  *       the rtems-libbsd tree already provides the remaining registers.
0254  */
0255
0256 #define BCM2711_EMMC_BASE           (RPI_PERIPHERAL_BASE + 0x300000)
0257
0258 /** @} */
0259
0260 /**
0261 * @name SPI Registers
0262 *
0263 * @{
0264 */
0265
0266 #define BCM2711_SPI0_BASE           (RPI_PERIPHERAL_BASE + 0x204000)
0267 #define BCM2711_SPI3_BASE           (RPI_PERIPHERAL_BASE + 0x204600)
0268 #define BCM2711_SPI4_BASE           (RPI_PERIPHERAL_BASE + 0x204800)
0269 #define BCM2711_SPI5_BASE           (RPI_PERIPHERAL_BASE + 0x204A00)
0270 #define BCM2711_SPI6_BASE           (RPI_PERIPHERAL_BASE + 0x204C00)
0271
0272 /** @} */
0273
0274 /**
0275 * @name Mailbox Registers
0276 *
0277 * @{
0278 */
0279
0280 #define BCM2711_MBOX_BASE          (RPI_PERIPHERAL_BASE+0xB880)
0281
0282 #define BCM2711_MBOX_READ          (BCM2711_MBOX_BASE+0x00)
0283 #define BCM2711_MBOX_PEEK          (BCM2711_MBOX_BASE+0x10)
0284 #define BCM2711_MBOX_SENDER        (BCM2711_MBOX_BASE+0x14)
0285 #define BCM2711_MBOX_STATUS        (BCM2711_MBOX_BASE+0x18)
0286 #define BCM2711_MBOX_WRITE         (BCM2711_MBOX_BASE+0x20)
0287 #define BCM2711_MBOX_CONFIG        (BCM2711_MBOX_BASE+0x1C)
0288
0289 #define BCM2711_MBOX_RESPONSE      0x80000000
0290 #define BCM2711_MBOX_FULL          0x80000000
0291 #define BCM2711_MBOX_EMPTY         0x40000000
0292
0293 /** @} */
0294
0295 /**
0296 * @name Mailbox Channels
0297 *
0298 * @{
0299 */
0300
0301 /* Power Manager channel */
0302 #define BCM2711_MBOX_CHANNEL_PM         0
0303 /* Framebuffer channel */
0304 #define BCM2711_MBOX_CHANNEL_FB         1
0305  /* Virtual UART channel */
0306 #define BCM2711_MBOX_CHANNEL_VUART      2
0307  /* VCHIQ channel */
0308 #define BCM2711_MBOX_CHANNEL_VCHIQ      3
0309  /* LEDs channel */
0310 #define BCM2711_MBOX_CHANNEL_LED        4
0311  /* Button channel */
0312 #define BCM2711_MBOX_CHANNEL_BUTTON     5
0313  /* Touch screen channel */
0314 #define BCM2711_MBOX_CHANNEL_TOUCHS     6
0315
0316 #define BCM2711_MBOX_CHANNEL_COUNT      7
0317 /* Property tags (ARM <-> VC) channel */
0318 #define BCM2711_MBOX_CHANNEL_PROP_AVC   8
0319  /* Property tags (VC <-> ARM) channel */
0320 #define BCM2711_MBOX_CHANNEL_PROP_VCA   9
0321
0322 /** @} */
0323
0324
0325
0326 /**
0327  * @name Raspberry Pi 2 Interrupt Register Defines
0328  *
0329  * @{
0330  */
0331
0332 /* Timers interrupt control registers */
0333 #define BCM2711_CORE0_TIMER_IRQ_CTRL_BASE       0xFF800040
0334 #define BCM2711_CORE1_TIMER_IRQ_CTRL_BASE       0xFF800044
0335 #define BCM2711_CORE2_TIMER_IRQ_CTRL_BASE       0xFF800048
0336 #define BCM2711_CORE3_TIMER_IRQ_CTRL_BASE       0xFF80004C
0337
0338 #define BCM2711_CORE_TIMER_IRQ_CTRL(cpuidx) \
0339   (BCM2711_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))
0340
0341
0342 /**
0343  * @name Raspberry Pi 4 ARM_LOCAL registers
0344  *
0345  * @{
0346  */
0347
0348 #define BCM2711_LOCAL_REGS_BASE               0x4C0000000
0349 #define BCM2711_LOCAL_REGS_SIZE               0x100
0350
0351 #define BCM2711_LOCAL_ARM_CONTROL             (BCM2711_LOCAL_REGS_BASE + 0x00)
0352 #define BCM2711_LOCAL_CORE_IRQ_CONTROL        (BCM2711_LOCAL_REGS_BASE + 0x0c)
0353 #define BCM2711_LOCAL_PMU_CONTROL_SET         (BCM2711_LOCAL_REGS_BASE + 0x10)
0354 #define BCM2711_LOCAL_PMU_CONTROL_CLR         (BCM2711_LOCAL_REGS_BASE + 0x14)
0355 #define BCM2711_LOCAL_PERI_IRQ_ROUTE0         (BCM2711_LOCAL_REGS_BASE + 0x24)
0356 #define BCM2711_LOCAL_AXI_QUIET_TIME          (BCM2711_LOCAL_REGS_BASE + 0x30)
0357 #define BCM2711_LOCAL_LOCAL_TIMER_CONTROL     (BCM2711_LOCAL_REGS_BASE + 0x34)
0358 #define BCM2711_LOCAL_LOCAL_TIMER_IRQ         (BCM2711_LOCAL_REGS_BASE + 0x38)
0359
0360 #define BCM2711_LOCAL_TIMER_CNTRL0            (BCM2711_LOCAL_REGS_BASE + 0x40)
0361 #define BCM2711_LOCAL_TIMER_CNTRL1            (BCM2711_LOCAL_REGS_BASE + 0x44)
0362 #define BCM2711_LOCAL_TIMER_CNTRL2            (BCM2711_LOCAL_REGS_BASE + 0x48)
0363 #define BCM2711_LOCAL_TIMER_CNTRL3            (BCM2711_LOCAL_REGS_BASE + 0x4c)
0364
0365 #define BCM2711_LOCAL_MAILBOX_CNTRL0          (BCM2711_LOCAL_REGS_BASE + 0x50)
0366 #define BCM2711_LOCAL_MAILBOX_CNTRL1          (BCM2711_LOCAL_REGS_BASE + 0x54)
0367 #define BCM2711_LOCAL_MAILBOX_CNTRL2          (BCM2711_LOCAL_REGS_BASE + 0x58)
0368 #define BCM2711_LOCAL_MAILBOX_CNTRL3          (BCM2711_LOCAL_REGS_BASE + 0x5c)
0369
0370 #define BCM2711_LOCAL_IRQ_SOURCE0             (BCM2711_LOCAL_REGS_BASE + 0x60)
0371 #define BCM2711_LOCAL_IRQ_SOURCE1             (BCM2711_LOCAL_REGS_BASE + 0x64)
0372 #define BCM2711_LOCAL_IRQ_SOURCE2             (BCM2711_LOCAL_REGS_BASE + 0x68)
0373 #define BCM2711_LOCAL_IRQ_SOURCE3             (BCM2711_LOCAL_REGS_BASE + 0x6c)
0374
0375 #define BCM2711_LOCAL_FIQ_SOURCE0             (BCM2711_LOCAL_REGS_BASE + 0x70)
0376 #define BCM2711_LOCAL_FIQ_SOURCE1             (BCM2711_LOCAL_REGS_BASE + 0x74)
0377 #define BCM2711_LOCAL_FIQ_SOURCE2             (BCM2711_LOCAL_REGS_BASE + 0x78)
0378 #define BCM2711_LOCAL_FIQ_SOURCE3             (BCM2711_LOCAL_REGS_BASE + 0x7c)
0379
0380 /**
0381  * @name Raspberry Pi 4 Mailbox registers
0382  *
0383  * @{
0384  */
0385
0386
0387
0388 #define BCM2711_MAILBOX_00_WRITE_SET_BASE               0x4C000080
0389 #define BCM2711_MAILBOX_01_WRITE_SET_BASE               0x4C000084
0390 #define BCM2711_MAILBOX_02_WRITE_SET_BASE               0x4C000088
0391 #define BCM2711_MAILBOX_03_WRITE_SET_BASE               0x4C00008C
0392 #define BCM2711_MAILBOX_04_WRITE_SET_BASE               0x4C000090
0393 #define BCM2711_MAILBOX_05_WRITE_SET_BASE               0x4C000094
0394 #define BCM2711_MAILBOX_06_WRITE_SET_BASE               0x4C000098
0395 #define BCM2711_MAILBOX_07_WRITE_SET_BASE               0x4C00009C
0396 #define BCM2711_MAILBOX_08_WRITE_SET_BASE               0x4C0000A0
0397 #define BCM2711_MAILBOX_09_WRITE_SET_BASE               0x4C0000A4
0398 #define BCM2711_MAILBOX_10_WRITE_SET_BASE               0x4C0000A8
0399 #define BCM2711_MAILBOX_11_WRITE_SET_BASE               0x4C0000AC
0400 #define BCM2711_MAILBOX_12_WRITE_SET_BASE               0x4C0000B0
0401 #define BCM2711_MAILBOX_13_WRITE_SET_BASE               0x4C0000B4
0402 #define BCM2711_MAILBOX_14_WRITE_SET_BASE               0x4C0000B8
0403 #define BCM2711_MAILBOX_15_WRITE_SET_BASE               0x4C0000BC
0404
0405 #define BCM2711_MAILBOX_00_READ_CLEAR_BASE              0x4C0000C0
0406 #define BCM2711_MAILBOX_01_READ_CLEAR_BASE              0x4C0000C4
0407 #define BCM2711_MAILBOX_02_READ_CLEAR_BASE              0x4C0000C8
0408 #define BCM2711_MAILBOX_03_READ_CLEAR_BASE              0x4C0000CC
0409 #define BCM2711_MAILBOX_04_READ_CLEAR_BASE              0x4C0000D0
0410 #define BCM2711_MAILBOX_05_READ_CLEAR_BASE              0x4C0000D4
0411 #define BCM2711_MAILBOX_06_READ_CLEAR_BASE              0x4C0000D8
0412 #define BCM2711_MAILBOX_07_READ_CLEAR_BASE              0x4C0000DC
0413 #define BCM2711_MAILBOX_08_READ_CLEAR_BASE              0x4C0000E0
0414 #define BCM2711_MAILBOX_09_READ_CLEAR_BASE              0x4C0000E4
0415 #define BCM2711_MAILBOX_10_READ_CLEAR_BASE              0x4C0000E8
0416 #define BCM2711_MAILBOX_11_READ_CLEAR_BASE              0x4C0000EC
0417 #define BCM2711_MAILBOX_12_READ_CLEAR_BASE              0x4C0000F0
0418 #define BCM2711_MAILBOX_13_READ_CLEAR_BASE              0x4C0000F4
0419 #define BCM2711_MAILBOX_14_READ_CLEAR_BASE              0x4C0000F8
0420 #define BCM2711_MAILBOX_15_READ_CLEAR_BASE              0x4C0000FC
0421
0422
0423 /**
0424  * @name Raspberry Pi 4 ARM_C FIQ and IRQ registers
0425  *
0426  * @{
0427  */
0428
0429 #define BCM2711_ARMC_REGS_BASE                 (RPI_PERIPHERAL_BASE + 0xB200)
0430 #define BCM2711_ARMC_REGS_SIZE                 0x200
0431
0432 #define BCM2711_ARMC_IRQ0_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x00)
0433 #define BCM2711_ARMC_IRQ0_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x04)
0434 #define BCM2711_ARMC_IRQ0_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x08)
0435 #define BCM2711_ARMC_IRQ0_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x10)
0436 #define BCM2711_ARMC_IRQ0_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x14)
0437 #define BCM2711_ARMC_IRQ0_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x18)
0438 #define BCM2711_ARMC_IRQ0_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0x20)
0439 #define BCM2711_ARMC_IRQ0_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0x24)
0440 #define BCM2711_ARMC_IRQ0_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0x28)
0441
0442 #define BCM2711_ARMC_IRQ_STATUS0               (BCM2711_ARMC_REGS_BASE + 0x30)
0443 #define BCM2711_ARMC_IRQ_STATUS1               (BCM2711_ARMC_REGS_BASE + 0x34)
0444 #define BCM2711_ARMC_IRQ_STATUS2               (BCM2711_ARMC_REGS_BASE + 0x38)
0445
0446 #define BCM2711_ARMC_IRQ1_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x40)
0447 #define BCM2711_ARMC_IRQ1_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x44)
0448 #define BCM2711_ARMC_IRQ1_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x48)
0449 #define BCM2711_ARMC_IRQ1_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x50)
0450 #define BCM2711_ARMC_IRQ1_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x54)
0451 #define BCM2711_ARMC_IRQ1_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x58)
0452 #define BCM2711_ARMC_IRQ1_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0x60)
0453 #define BCM2711_ARMC_IRQ1_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0x64)
0454 #define BCM2711_ARMC_IRQ1_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0x68)
0455
0456 #define BCM2711_ARMC_IRQ2_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x80)
0457 #define BCM2711_ARMC_IRQ2_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x84)
0458 #define BCM2711_ARMC_IRQ2_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x88)
0459 #define BCM2711_ARMC_IRQ2_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x90)
0460 #define BCM2711_ARMC_IRQ2_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x94)
0461 #define BCM2711_ARMC_IRQ2_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x98)
0462 #define BCM2711_ARMC_IRQ2_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0xA0)
0463 #define BCM2711_ARMC_IRQ2_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0xA4)
0464 #define BCM2711_ARMC_IRQ2_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0xA8)
0465
0466 #define BCM2711_ARMC_IRQ3_PENDING0             (BCM2711_ARMC_REGS_BASE + 0xC0)
0467 #define BCM2711_ARMC_IRQ3_PENDING1             (BCM2711_ARMC_REGS_BASE + 0xC4)
0468 #define BCM2711_ARMC_IRQ3_PENDING2             (BCM2711_ARMC_REGS_BASE + 0xC8)
0469 #define BCM2711_ARMC_IRQ3_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0xD0)
0470 #define BCM2711_ARMC_IRQ3_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0xD4)
0471 #define BCM2711_ARMC_IRQ3_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0xD8)
0472 #define BCM2711_ARMC_IRQ3_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0xE0)
0473 #define BCM2711_ARMC_IRQ3_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0xE4)
0474 #define BCM2711_ARMC_IRQ3_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0xE8)
0475
0476
0477
0478 #define BCM2711_ARMC_FIQ0_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x100)
0479 #define BCM2711_ARMC_FIQ0_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x104)
0480 #define BCM2711_ARMC_FIQ0_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x108)
0481 #define BCM2711_ARMC_FIQ0_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x110)
0482 #define BCM2711_ARMC_FIQ0_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x114)
0483 #define BCM2711_ARMC_FIQ0_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x118)
0484 #define BCM2711_ARMC_FIQ0_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0x120)
0485 #define BCM2711_ARMC_FIQ0_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0x124)
0486 #define BCM2711_ARMC_FIQ0_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0x128)
0487
0488 #define BCM2711_ARMC_FIQ1_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x140)
0489 #define BCM2711_ARMC_FIQ1_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x144)
0490 #define BCM2711_ARMC_FIQ1_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x148)
0491 #define BCM2711_ARMC_FIQ1_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x150)
0492 #define BCM2711_ARMC_FIQ1_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x154)
0493 #define BCM2711_ARMC_FIQ1_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x158)
0494 #define BCM2711_ARMC_FIQ1_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0x160)
0495 #define BCM2711_ARMC_FIQ1_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0x164)
0496 #define BCM2711_ARMC_FIQ1_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0x168)
0497
0498 #define BCM2711_ARMC_FIQ2_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x180)
0499 #define BCM2711_ARMC_FIQ2_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x184)
0500 #define BCM2711_ARMC_FIQ2_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x188)
0501 #define BCM2711_ARMC_FIQ2_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x190)
0502 #define BCM2711_ARMC_FIQ2_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x194)
0503 #define BCM2711_ARMC_FIQ2_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x198)
0504 #define BCM2711_ARMC_FIQ2_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0x1A0)
0505 #define BCM2711_ARMC_FIQ2_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0x1A4)
0506 #define BCM2711_ARMC_FIQ2_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0x1A8)
0507
0508 #define BCM2711_ARMC_FIQ3_PENDING0             (BCM2711_ARMC_REGS_BASE + 0x1C0)
0509 #define BCM2711_ARMC_FIQ3_PENDING1             (BCM2711_ARMC_REGS_BASE + 0x1C4)
0510 #define BCM2711_ARMC_FIQ3_PENDING2             (BCM2711_ARMC_REGS_BASE + 0x1C8)
0511 #define BCM2711_ARMC_FIQ3_SET_EN_0             (BCM2711_ARMC_REGS_BASE + 0x1D0)
0512 #define BCM2711_ARMC_FIQ3_SET_EN_1             (BCM2711_ARMC_REGS_BASE + 0x1D4)
0513 #define BCM2711_ARMC_FIQ3_SET_EN_2             (BCM2711_ARMC_REGS_BASE + 0x1D8)
0514 #define BCM2711_ARMC_FIQ3_CLR_EN_0             (BCM2711_ARMC_REGS_BASE + 0x1E0)
0515 #define BCM2711_ARMC_FIQ3_CLR_EN_1             (BCM2711_ARMC_REGS_BASE + 0x1E4)
0516 #define BCM2711_ARMC_FIQ3_CLR_EN_2             (BCM2711_ARMC_REGS_BASE + 0x1E8)
0517
0518 #define BCM2711_ARMC_SWIRQ_SET                 (BCM2711_ARMC_REGS_BASE + 0x1F0)
0519 #define BCM2711_ARMC_SWIRQ_CLEAR               (BCM2711_ARMC_REGS_BASE + 0x1F4)
0520
0521
0522
0523
0524
0525 /** @} */
0526
0527 #endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */