dev/irq/arm-gic-arch.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup DevIRQGIC
0007  *
0008  * @brief This header file provides interfaces of the ARM Generic Interrupt
0009  *   Controller (GIC) support specific to the AArch64 architecture.
0010  */
0011
0012 /*
0013  * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
0014  * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
0015  *
0016  * Redistribution and use in source and binary forms, with or without
0017  * modification, are permitted provided that the following conditions
0018  * are met:
0019  * 1. Redistributions of source code must retain the above copyright
0020  *    notice, this list of conditions and the following disclaimer.
0021  * 2. Redistributions in binary form must reproduce the above copyright
0022  *    notice, this list of conditions and the following disclaimer in the
0023  *    documentation and/or other materials provided with the distribution.
0024  *
0025  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0026  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0027  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0028  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0029  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0030  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0031  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0032  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0033  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0034  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0035  * POSSIBILITY OF SUCH DAMAGE.
0036  */
0037
0038 #ifndef _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
0039 #define _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
0040
0041 #include <rtems/score/cpu.h>
0042 #include <rtems/score/cpu_irq.h>
0043
0044 #include <bsp/irq-generic.h>
0045
0046 #ifdef __cplusplus
0047 extern "C" {
0048 #endif
0049
0050 /**
0051  * @addtogroup DevIRQGIC
0052  *
0053  * @{
0054  */
0055
0056 static inline uint32_t arm_interrupt_enable_interrupts(void)
0057 {
0058   uint32_t status = _CPU_ISR_Get_level();
0059   /* Enable interrupts for nesting */
0060   _CPU_ISR_Set_level(0);
0061   return status;
0062 }
0063
0064 static inline void arm_interrupt_restore_interrupts(uint32_t status)
0065 {
0066   /* Restore interrupts to previous level */
0067   _CPU_ISR_Set_level(status);
0068 }
0069
0070 static inline void arm_interrupt_facility_set_exception_handler(void)
0071 {
0072   AArch64_set_exception_handler(
0073     AARCH64_EXCEPTION_SPx_IRQ,
0074     _AArch64_Exception_interrupt_no_nest
0075   );
0076   AArch64_set_exception_handler(
0077     AARCH64_EXCEPTION_SP0_IRQ,
0078     _AArch64_Exception_interrupt_nest
0079   );
0080 }
0081
0082 /** @} */
0083
0084 #ifdef __cplusplus
0085 }
0086 #endif
0087
0088 #endif /* _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H */